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QE1M Device
Quad E1 Mapper TXC-04252 DATA SHEET FEATURES
* Add/drop four 2.048 Mbit/s signals from STM-1/VC-4, STS-3/AU-3 or STS-1 buses * Independent add and drop bus timing modes * Selectable HDB3 positive/negative rail or NRZ E1 interface. Performance counter provided for coding violations. * Digital desynchronizer * Drop buses are monitored for parity, loss of clock, upstream AIS and H4 multiframe errors * Performance counters are provided for TU/VT pointer movements, BIP-2 errors and Far End Block Errors (FEBEs) * TU/VTs are monitored for Loss Of Pointer, New Data Flags (NDFs), AIS, Remote Defect Indication (RDI), and size errors (S-bits) * V5 Byte Signal Label Mismatch and Unequipped detection * E1 facility and line loopbacks, generation of BIP-2 and FEBE errors, and send RDI capability * Intel / Motorola / Multiplexed-compatible microprocessor bus interface with interrupt capability * Programmable internal RISC processor implements VT-POH and VT-alarm handling * J2 16-byte ETSI trail trace comparison * Optional V4 receive and transmit byte access * TU tandem connection processing (N2 byte) * IEEE 1149.1 standard boundary scan * Single +5 V 5 % power supply * 160-lead plastic quad flat package or 208-lead PBGA (17 mm x 17 mm)
DESCRIPTION
The Quad E1 Mapper device is designed for add/drop multiplexer, terminal multiplexer, and dual and single unidirectional ring applications. Four E1 2.048 Mbit/s signals are mapped to and from asynchronous Tributary Unit-12 (TU-12) or Virtual Tributary 2 (VT2) formats. The QE1M interfaces to a multiple-segment, byte-parallel SDH/SONET-formatted bus at the 19.44 Mbit/s byte rate for STM-1/STS-3 operation or at the 6.48 Mbit/s byte rate for STS-1 operation. The E1 2.048 Mbit/s signals can be either HDB3 positive/negative rail- or NRZ-formatted signals. The QE1M provides performance counters, alarm detection, and the ability to generate errors and Alarm Indication Signals (AIS). E1 facility and line loopback capabilities are also provided. The QE1M bus interface is used to connect to other TranSwitch devices such as the STM-1/STS-3/STS-3c Overhead Terminator (SOT-3), TXC-03003 or TXC-03003B, to form an STM-1/STS-3 add/drop or terminal system.
APPLICATIONS
* STM-1/STS-3/STS-1 to 2.048 Mbit/s add/drop mux/demux * Unidirectional or bidirectional ring applications * STM-1/STS-3/STS-1 termination terminal mode multiplexer * STM-1/STS-3/STS-1 test equipment
STM-1/STS-3/STS-1 SDH/SONET SIDE
A - side drop bus A - side add bus B - side drop bus B - side add bus
+5V 13 14 13 14 5 Boundary Scan
External Clock
2.048 Mbit/s LINE SIDE
7 Port 1
QE1M Quad E1 Mapper TSC-04252
3 Microprocessor interface Controls
7 Port 2 7 Port 3 7 Port 4
P & N data and clock for receive and transmit, plus receive data zero-output control
U.S. Patents No. 4,967,405; 5,033,064; 5,040,170; 5,265,096; 5,289,057; 5,297,180; 5,473,611; 5,528,598; 5,535,218; U.S. and/or foreign patents issued or pending Copyright 2000 TranSwitch Corporation TranSwitch and TXC are registered trademarks of TranSwitch Corporation
Document Number: TXC-04252-MB Ed. 3, December 2000
TranSwitch Corporation * 3 Enterprise Drive * Shelton, Connecticut 06484 Tel: 203-929-8810 * Fax: 203-926-9453 * www.transwitch.com
*
USA
Proprietary TranSwitch Corporation Information for use Solely by its Customers.
Proprietary TranSwitch Corporation Information for use Solely by its Customers.
QE1M TXC-04252
DATA SHEET
TABLE OF CONTENTS
Section Page
List of Figures ..................................................................................................................................... 3 Block Diagram ................................................................................................................................... 4 Block Diagram Description ................................................................................................................ 5 Lead Diagrams .................................................................................................................................. 9 Lead Descriptions ............................................................................................................................ 11 Absolute Maximum Ratings and Environmental Limitations ........................................................... 21 Thermal Characteristics ................................................................................................................... 21 Power Requirements ....................................................................................................................... 21 Input, Output and Input/Output Parameters .................................................................................... 22 Timing Characteristics ..................................................................................................................... 25 Operation ......................................................................................................................................... 43 Bus Interface Modes ................................................................................................................ 43 Bus Mode Selection ................................................................................................................. 44 SDH/SONET Add/Drop Multiplexing Format Selections .......................................................... 44 Drop TU/VT Selection .............................................................................................................. 45 Add TU/VT Selection ................................................................................................................ 46 Bus Timing ............................................................................................................................... 47 Unequipped Operation ............................................................................................................. 47 Drop Bus Multiframe Alignment ................................................................................................ 49 Add Bus Multiframe Alignment ................................................................................................. 50 Performance Counters ............................................................................................................. 51 Alarm Structure ........................................................................................................................ 51 Interrupt Structure .................................................................................................................... 52 SDH/SONET AIS Detection ..................................................................................................... 58 TU/VT Pointer Tracking ............................................................................................................ 59 Remote Defect Indications ....................................................................................................... 61 Overhead Communications Bit Access .................................................................................... 64 BIP-2, AIS Indication, TC REI and TC OEI Processing ............................................................ 68 TUG-3 Null Pointer Indicator .................................................................................................... 70 E1 Loopback Capability ........................................................................................................... 71 PRBS Pattern Generator and Analyzer .................................................................................... 72 Resets ...................................................................................................................................... 72 Start-Up Procedure .................................................................................................................. 73 Pointer Leak Rate Calculations ................................................................................................ 74 Jitter Measurements ................................................................................................................. 75 Internal Spot Processor ............................................................................................................ 80 Boundary Scan ......................................................................................................................... 84 Multiplex Format and Mapping Information .............................................................................. 93 Memory Map ................................................................................................................................... 99 Memory Map Descriptions ............................................................................................................. 105 Package Information ..................................................................................................................... 138 Ordering Information ..................................................................................................................... 140
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DATA SHEET
QE1M TXC-04252
Related Products ........................................................................................................................... 140 Standards Documentation Sources .............................................................................................. 141 List of Data Sheet Changes .......................................................................................................... 143 Documentation Update Registration Form *.............................................................................. 147 * Please note that TranSwitch provides documentation for all of its products. Customers who are using a TranSwitch Product, or planning to do so, should register with the TranSwitch Marketing Department to receive relevant updated and supplemental documentation as it is issued. They should also contact the Applications Engineering Department to ensure that they are provided with the latest available information about the product, especially before undertaking development of new designs incorporating the product.
LIST OF FIGURES
Figure
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29.
Page
QE1M TXC-04252 Block Diagram......................................................................................... 4 2048 kbit/s Asynchronous Mapping....................................................................................... 8 QE1M TXC-04252 Plastic Quad Flat Package Lead Diagram .............................................. 9 QE1M TXC-04252 Plastic Ball Grid Array Package Lead Diagram..................................... 10 Ports 1, 2, 3 and 4 E1 Transmit Timing ............................................................................... 25 Ports 1, 2, 3 and 4 E1 Receive Timing ................................................................................ 26 STS-1 A/B Drop and Add Bus Signals, Timing Derived from Drop Bus .............................. 27 STM-1/STS-3 A/B Drop and Add Bus Signals, Timing Derived from Drop Bus .................. 28 STS-1 A/B Add Bus Signals, Timing Derived from Add Bus ............................................... 29 STM-1/STS-3 A/B Add Bus Signals, Timing Derived from Add Bus.................................... 30 Microprocessor Read Cycle Timing - Multiplex Bus ............................................................ 31 Microprocessor Write Cycle Timing - Multiplex Bus ............................................................ 33 Microprocessor Read Cycle Timing - Intel........................................................................... 35 Microprocessor Write Cycle Timing - Intel ........................................................................... 37 Microprocessor Read Cycle Timing - Motorola.................................................................... 38 Microprocessor Write Cycle Timing - Motorola ................................................................... 40 Boundary Scan Timing ........................................................................................................ 42 H4 Byte Floating VT Mode Bit Allocation............................................................................. 49 TU/VT Pointer Tracking State Machine ............................................................................... 60 Facility and Line Loopbacks ................................................................................................ 71 Jitter Tolerance and Jitter Test Arrangements..................................................................... 76 Jitter Tolerance Measurements ........................................................................................... 76 Jitter Transfer Measurements.............................................................................................. 77 Standard Pointer Test Sequences....................................................................................... 79 Schematic Diagram of QE1M Showing SPOT Processor Interfaces................................... 82 Recommended Implementation Flowchart for Reprogramming the SPOT Processor ........ 83 Boundary Scan Schematic .................................................................................................. 85 QE1M TXC-04252 160-Lead Plastic Quad Flat Package.................................................. 138 QE1M TXC-04252 208-Lead Plastic Ball Grid Array Package .......................................... 139
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QE1M TXC-04252 BLOCK DIAGRAM
DATA SHEET
SDH/SONET SIDE
12 TU/VT A Receive (A Drop) 1 Terminate A Side Repeated for Ports 1, 2, 3 and 4
EXTCK
QUIETn
RPOn RNOn Destuff Desync
*
HDB3 Coder
RCOn
12 B Receive (B Drop) 1 TU/VT Terminate B Side Mux, Intel/Motorola functions: Symbols Mux mode select: MUX 3 8 SPOT RISC P 8 Motorola mode select: MOTO Add., Add.: UPA(10-8), A(10-8) Add. & Data, Add.: UPAD(7-0), A(7-0) NU*, Data: NU*, D(7-0) Select, Select: SEL, SEL Alarms & Controls I/O Read, Read / Read/Write: RD, RD / RD/WR Write, Write/Select: WR,WR/LDS Add. Latch Enable, NU*: ALE, NU* Ready, Ready/DT Ack: RDY, RDY/DTACK Alarms Controls, & Timing 3 A Transmit (A Add) 11 Interrupt, Interrupt: INT, INT/IRQ Interrupt Sense Select: INTSH, INTSH
*
LINE SIDE
13 14
13 14
Processor and RAM
*
TU/VT Build A Side
*
*
Stuff/Sync A Side
* Note: NU=lead not used in this mode
*
HDB3 Decoder
*
TPIn TNIn/TLOSn TCIn
A Drop
B Drop
A Add
B Add
3 B Transmit (B Add) 11 Repeated for Ports 1, 2, 3 and 4 TU/VT Build B Side Stuff/Sync B Side
LINE SIDE
TCK IEEE 1149.1 Boundary Scan Input/Output TMS TDI TDO TRS
TEST
Test Access Port
ABUST HIGHZ RESET
Figure 1. QE1M TXC-04252 Block Diagram
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DATA SHEET BLOCK DIAGRAM DESCRIPTION
QE1M TXC-04252
The block diagram for the Quad E1 Mapper is shown in 1. The Quad E1 Mapper interfaces to four buses, designated as A Drop, B Drop, A Add, and B Add. The four buses run at the STM-1/STS-3 rate of 19.44 Mbyte/s, or at the STS-1 rate of 6.48 Mbyte/s. For North American applications, the asynchronous E1 signals are carried in floating Virtual Tributary 2 (VT2) format in a Synchronous Transport Signal - 1 (STS-1), or in an STS-1 that is carried in a Synchronous Transport Signal - 3 (STS-3). For ITU-T applications, the E1 signals are carried in floating mode Tributary Unit - 12 (TU-12) format in the STM-1 Virtual Container - 4 structure (VC-4) using Tributary Unit Group - 3 (TUG-3), or in the STM-1 Virtual Container - 3 structure (VC-3) using Tributary Unit Group -2 (TUG-2) mapping schemes. Four E1 signals can be dropped from one bus (A Drop or B Drop), or from both of the drop buses, to the E1 lines. Four asynchronous E1 signals are converted into TU-12 or VT2 format and are added to either of the add buses, or both, depending upon the mode of operation. When the Quad E1 Mapper is configured for droP bus timing, the add buses are, by definition, byte- and multiframe-synchronous with their like-named drop buses, but are delayed by one byte time because of internal processing. For example, if a byte in the STM-1 Virtual Container - 4 structure (VC-4) using Tributary Unit Group - 3 (TUG-3), TU-12/VT2 is to be added to the A Add bus, the time of its placement on the bus is derived from the A Drop bus timing, and from software instructions specifying which TU/VT number is being dropped/added. When the device is configured for add bus timing, the add bus, parity, and add indicator signals are derived from the add clock, C1J1V1 and SPE signals. The A Receive block is identical to the B Receive block. The TU/VT Terminate block is repeated 8 times, two for each port (A and B sides). The Destuff, Desync, and HDB3 Coder blocks are repeated four times, one for each port. The interface between a drop bus and Receive block consists of 12 input leads, and an optional output lead: a byte clock, byte-wide data, a C1J1 indicator which may be carrying a V1 indication making the signal a C1J1V1 indicator, an SPE indicator, and an odd parity bit for the last-named three signals. Parity is selectable by control bits for even parity and for the data byte only. The output lead is an optional TU/VT select indicator signal. The Drop C1J1V1 signal is used in conjunction with the Drop SPE signal to determine the location of the various pulses. The C1 pulse identifies the location of the C1 byte when the SPE signal is low. A single J1 pulse identifies the starting location of the J1 byte in the VC-4 format, when the SPE signal is high. Three J1 pulses are provided for the STS-3 format, each identifying the starting location of the J1 byte in each of the STS-1 signals. The Quad E1 Mapper can operate with a V1 pulse in the C1J1V1 signal, or it can use an internal H4 detector for determining the location of the V1 pulse. The V1 pulse location is used to determine the location of the pointer byte V1. For STM-1 VC-4 operation, if the C1J1V1 signal is used, a single V1 pulse must occur three drop bus clock cycles every four frames following the J1 pulse when the SPE signal is high. For STS-3 operation, three V1 pulses must be present every four frames. Each of the three V1 pulses must be present three clock cycles after the corresponding J1 pulse, when the SPE signal is high. For example, in a VC-4 signal, the J1 pulse identifies the J1 byte location (defined as the starting location for the VC-4) in the POH bytes. In the next column (first clock cycle) all the rows are assigned as fixed stuff. Similarly, in the next column (second clock cycle) all the rows are assigned as fixed stuff. The next column (third clock cycle) defines the start of TUG-3 A. This column is where the V1 pulse occurs every four frames. However, the actual V1 byte location is six clock cycles after the V1 pulse. For STS-1 operation, one V1 pulse must be present if the C1J1V1 signal is used. The V1 pulse must occur on the next clock cycle after the J1 pulse, and when the SPE signal is high. The J1 pulse identifies the J1 byte location (defined as the starting location for the STS-1) in the POH bytes. In the next column (first clock cycle) the TUs start. Thus, the V1 pulse identifies the starting location of the first V1 byte in the signal. The rest of the V1 bytes for the 21 TU-12/VT2s are also aligned with respect to the V1 pulse (please see the first diagram in the Operation - Multiplex Format and Mapping Information section). Each bus is monitored for parity errors, loss of clock, H4 multiframe alignment if selected, and an upstream SDH/SONET AIS indication. The Quad E1 Mapper can monitor either the TOH E1 bytes or the H1/H2 bytes for an AIS indication. Which E1 byte and H1/H2 bytes are selected is a function of the TU/VT selected.
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QE1M TXC-04252
DATA SHEET
Each TU/VT Terminate block (A and B side) performs pointer processing based on the location of the V1 and V2 bytes. The pointer bytes are monitored for loss of pointer, TU AIS indication, and NDF. The pointer tracking process is based on the latest ETSI standard, which also meets ANSI/Bellcore requirements. Pointer increments and decrements are also counted, and the SS-bits are monitored for the correct value. This block also monitors the various alarms found in the V5 and K4 (formerly known as Z7) bytes, including signal label mismatch detection, unequipped status detection, BIP-2 parity error detection and error counter, FEBE counter, and the three RDI indications. The Quad E1 Mapper performs a 16-byte J2 trail trace comparison on the channels selected. For 64-byte messages, the bytes are stored in a memory map segment for a microprocessor read cycle. The device also provides the TU tandem connection feature and performs the 16-byte message comparison for the N2 (formerly known as Z6) byte message. A control bit for each port selects the TU/VT from either the A Drop or B Drop bus. The TU/VT is destuffed in the Destuff block using majority logic rules for the three sets of three justification control bits to determine if the two S-bits are data bits or frequency justification bits. The Desync block removes the effects on the E1 output of systemic jitter that might occur because of signal mappings and pointer movements in the network. The Desync block contains two parts, a pointer leak buffer, and a E1 loop buffer. The pointer leak buffer can accept up to five consecutive pointer movements, and can adjust the effect over time. The E1 Loop Buffer consists of a digital loop filter, which is designed to track the frequency of the received E1 signal and to remove both transmission and stuffing jitter. An option for each port provides either NRZ data, or an HDB3-encoded positive and negative rail signal for the E1 interface. Receive data (towards the E1 line), for all four channels, can be clocked out on either rising or falling edges of the clock. In addition, control bits are provided for forcing the data and clock signals to a high impedance state (tristate). A control lead is provided for forcing the output leads to the 0 state. In the add direction, the Quad E1 Mapper accepts clock and either NRZ data or HDB3-encoded positive and negative rail signals. Data, for all four channels, can be clocked in on either the falling or rising edge of the clock. In the NRZ mode, an external loss of clock indication input signal can be provided. For the rail signal, coding violations are counted, and there is monitoring for loss of signal. An E1AIS detector is also provided. The data signal is written into a FIFO in one of the eight Stuff/Sync blocks. Threshold modulation is used for the frequency justification process. Timing information from the drop bus or add bus is used to read the FIFO and perform the TU/VT justification process. This block permits tracking of an incoming E1 signal having an average frequency offset as high as 120 ppm, and up to 1.5 UI of peak-to-peak jitter. Since the Quad E1 Mapper supports a ring architecture, two sets of blocks are provided for each port. The TU/VT selection is the same for both blocks. A control bit, and transmit line alarms, can generate an E1AIS. The eight TU/VT Build blocks format the TU/VT into a STS-1, STS-3 or STM-1 structure for the asynchronous 2048 kbit/s signals, as shown in 2. The pointer value carried in the V1 and V2 bytes is transmitted with a fixed value of 105. Transmit access is provided for the 8 overhead communications channel bits (O-bits) via the microprocessor. The microprocessor also writes the signal label, and the value of the J2 message, either as a 16-byte or a 64-byte message. The Quad E1 Mapper provides the TU tandem connection feature for the TU, including the transmission of the 16-byte message and the various alarms associated with the tandem connection feature. The device provides three-bit RDI using the V5 and K4 (Z7) bytes. Local alarms, or the microprocessor, can generate the remote payload, server, or connectivity defect indications. The Far End Block Error (FEBE) is inserted from the BIP-2 errors detected on the receive side, and BIP-2 parity is generated for the V5 byte. Control bits are provided for generating unequipped status, generating TU/VT AIS, and inserting FEBE and BIP-2 errors. The ability to generate Null Pointer Indicators (NPIs) is also provided for the STM-1 VC-4 format. The A Transmit block is identical to the B Transmit block. The interface between an add bus and a Transmit block consists of three input leads and eleven output leads, when the add bus timing mode is selected. The input leads are a byte clock, a C1J1V1 indicator, and an SPE indicator. The output leads are byte-wide data, a parity indicator, an add indicator, and an optional TU/VT selection indicator signal. The Add C1J1V1 signal is used in conjunction with the Add SPE signal to determine the location of the various pulses. An option is pro-
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DATA SHEET
QE1M TXC-04252
vided in which the drop side V1 reference pulse, either from the drop bus C1J1V1 indicator or from the H4 multiframe detector, may be used as the add side V1 reference pulse. When drop bus timing is selected, the output leads are byte-wide data, a parity indicator, an add indicator, and an optional TU/VT selection indicator signal. The add bus clock, SPE and C1J1V1 signals are disabled. The Microprocessor Input/Output Interface block consists of an Intel-, Motorola- or multiplexed address/data-compatible bus interface that provides access to assigned QE1M memory map addresses in the range from 000H to 7FFH (please see the Memory Map and Memory Map Description sections for further information). Interrupt capability is also provided. The alarms that cause the interrupt can be set on positive, negative, or both positive and negative transitions, or on positive levels. Interrupt mask bits are provided for register byte locations, and some defined bits. Control bits are provided which enable an E1 facility or line loopback. Because of the complexity of the SDH/SONET interface and the two timing modes, SDH/SONET loopback of the TU/VTs is not supported. The SPOT (SONET Processor for Overhead Termination) block is a RISC processor with associated instruction and data memory that performs selected low-speed functions, including all overhead processing and counter maintenance. The SPOT program must be loaded into the SPOT instruction memory after power-up. Executable microcode is provided by TranSwitch (see the Operations - Internal SPOT Processor section). The Boundary Scan Interface Block provides a five-lead Test Access Port (TAP) that conforms to the IEEE 1149.1 standard. This standard provides external boundary scan functions to read and write the external Input/Output leads from the TAP for board and component test.
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QE1M TXC-04252
DATA SHEET
VC-12 V5 RRRRRRRR 32 bytes (2048 kbit/s Data) RRRRRRRR J2 C1 C2 O O O O R R 32 bytes (2048 kbit/s Data) RRRRRRRR N2 (Z6) C1 C2 O O O O R R 32 bytes (2048 kbit/s Data) RRRRRRRR K4 (Z7) C1 C2 R R R R R S1 S2 I I I I I I I 31 bytes (2048 kbit/s Data) RRRRRRRR 140 Bytes Path Overhead (V5) Byte BIP-2 1 BIT 1 BIP-2 = Bit Interleaved Parity (2 bits) REI = Remote Error Indication (formerly FEBE, Far End Block Error Indication) RFI = Remote Failure Indication L1L2L3 = Signal Label RDI = Remote Defect Indication (formerly FERF, Far End Receive Failure Indication) V1 REI
(FEBE)
TU-12/VT2 V1 (Pointer Byte)
35 bytes
V2 (Pointer Byte)
35 bytes
V3 (Action)
I = Information O = Overhead communications Cn = Justification control Sn = Justification opportunity R = Fixed stuff (set to 0)
35 bytes
V4 (Reserved)
500 s
35 bytes
144 Bytes RDI
(FERF)
RFI
L1
L2 L3 Signal Label
8 V2
NDF
S1 S2 I
D
I
D
I
D
I
D
I
D
New Data Flag Normal = 0110, 1110, 0010, 0100 or 0111 New = 1001, 0001, 1101, 1011 or 1000 Positive Justification = Invert five I-bits Negative Justification = Invert five D-bits Pointer Range = 0 - 139 decimal
Size S1S2 = 10
Figure 2. 2048 kbit/s Asynchronous Mapping
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DATA SHEET LEAD DIAGRAMS
QE1M TXC-04252
95
90
85
GND QUIET4 TCI4 TNI4/TLOS4 TPI4 VDD RCO4 RNO4 RPO4 RCO2 RNO2 RPO2 GND QUIET2 TCI2 TNI2/TLOS2 TPI2 VDD BAIND BDIND GND BDCLK BACLK GND BAC1J1V1 BASPE BDC1J1V1 BDSPE VDD BDPAR BD7 BD6 BD5 BD4 VDD BD3 BD2 BD1 BD0 GND
10
15
20
25
30
35
Figure 3. QE1M TXC-04252 Plastic Quad Flat Package Lead Diagram
UPA10 (A10) MOTO MUX GND QUIET3 TCI3 TNI3/TLOS3 TPI3 VDD RCO3 RNO3 RPO3 VDD RCO1 RNO1 RPO1 GND QUIET1 TCI1 TNI1/TLOS1 TPI1 VDD AAIND ADIND GND ADCLK GND AACLK GND AAC1J1V1 AASPE ADC1J1V1 ADSPE VDD TRS TMS TDO TDI TCK GND
Note: See Figure 28 for Package Information. X(Y/Z) format is used for microprocessor interface signals to identify Multiplex (Intel/Motorola) interface functions, where these are different.
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40
TEST RDY (RDY/DTACK) VDD UPAD0 (D0) UPAD1 (D1) UPAD2 (D2) GND UPAD3 (D3) UPAD4 (D4) UPAD5 (D5) VDD UPAD6 (D6) UPAD7 (D7) GND A0 HIGHZ VDD EXTCK GND A1 A2 VDD A3 A4 TEST SEL RD (RD / RD/WR) WR (WR/LDS) ALE (Not Used) INTSH GND INT (INT/IRQ) A5 VDD RESET A6 ABUST A7 UPA8 (A8) UPA9 (A9)
80
125 75
130 70
135 65
140
QE1M Lead Diagram (Top View) TXC-04252
60
145 55
150 50
155 45
NC VDD BADD BAPAR BA7 BA6 GND BA5 BA4 BA3 VDD BA2 BA1 BA0 GND AA0 AA1 AA2 AA3 GND AA4 AA5 AA6 VDD AA7 AAPAR AADD GND AD0 AD1 AD2 VDD AD3 AD4 AD5 GND AD6 AD7 ADPAR VDD
120
115
110
105
1
5
100
Proprietary TranSwitch Corporation Information for use Solely by its Customers.
QE1M TXC-04252
DATA SHEET
VDD
BD1
BD3
BD4
BD7
BDC1J1V1 BACLK
NC
NC
QUIET2
RNO2
NC
VDD
TPI4
NC
TCI4 16
NC
NC
BD2
VDD
BD6
BDSPE
NC
GND
TPI2
NC
NC
RNO4
NC
TNI4
QUIET4 RDY/DTACK 15 NC VDD 14
BAPAR
BADD
BD0
NC
BDPAR BASPE
BDCLK
BDIND
VDD
TCI2
RPO2
RPO4
RCO4
TEST
BA7
BA6
GND
BD5
VDD
BAC1J1V1
NC
BAIND
NC
TNI2
NC
RCO2
GND
UPAD1
UPAD0
UPAD2 13
BA4
BA5
BA3
VDD
NC
UPAD5
UPAD3 UPAD4 12
BA2
NC
BA1
BA0
UPAD7 UPAD6
VDD
NC 11
AA0
NC
AA1
AA2
NC
GND
NC
GND
EXTCK
VDD
A0
HIGHZ 10
GND
AA3
NC
AA4
GND
GND
GND
GND
VDD
A2
A1
GND 9
NC
VDD
AA6
AA5
GND
GND
GND
GND
A3
A4
SEL
TEST 8
AAPAR
AADD
AA7
NC
NC
GND
NC
GND
RD
WR
INTSH
ALE 7
AD2
VDD
AD1
AD0
INT/IRQ
A5
VDD
NC 6
AD5
NC
AD4
AD3
NC
RESET
A6
NC 5
NC
AD7
AD6
GND
NC
AAC1J1V1
GND
NC
VDD
TNI1
RPO1
RPO3
TPI3
NC
NC
ABUST 4
ADPAR
NC
NC
NC
ADSPE
NC
ADCLK
AAIND
NC
NC
RN01
RNO3 TCI3
UPA10
NC
A7 3
VDD
TCK
NC
TMS
VDD ADC1J1V1 AACLK ADIND
NC
QUIET1
VDD
VDD
QUIET3
GND
UPA9
UPA8 2
NC
TDI
TDO
TRS
NC
AASPE
GND
NC
TPI1
TCI1
RCO1
RCO3
TNI3
MUX
MOTO
NC 1
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
Note:
This is the bottom view. The leads are solder balls. See Figure 29 for package information. Some signal Symbols have been abbreviated to fit the space available. The Symbols are shown in full in the Lead Descriptions section.
Figure 4. QE1M TXC-04252 Plastic Ball Grid Array Package Lead Diagram
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DATA SHEET LEAD DESCRIPTIONS
POWER SUPPLY, GROUND AND NO CONNECT Symbol 160-Lead PQFP Lead No. 208-Lead PBGA Lead No. I/O/P * Type Name/Function VDD: +5 volt supply voltage, 5%.
QE1M TXC-04252
VDD
A14, B6, 9, 13, 22, B11, C10, 34, 41, 49, D9, D16, 57, 70, 79, 86, 92, 103, E2, F2, H4, H14, M2, 115, 123, M13, N12, 131, 137, N15, R6, 142, 154 R8, T2, T16 4, 17, 25, 27, 29, 40, 45, 53, 61, 66, 74, 81, 97, 100, 108, 120, 127, 134, 139, 151 80 A9, C2, D13, G7, G8, G9, G10, H8, H9, J7, J8, J9, J10, J15, K1, K4, K8, K9, N4, P13, T9 A1, A5, A6, A11, B3, B4, B14, B16, C4, D5, D12, D15, E16, F13, F15, G3, G15, H2, H3, H7, H10, H13, H16, J1, J4, J16, K7, K10, K13, K15, L3, M1, M4, N3, N7, N14, P2, P3, P9, R3, R5, R10, R11, R15, T1, T4, T8, T15
P
GND
P
Ground: 0 volt reference.
NC
No Connect: NC leads are not to be connected, not even to another NC lead, but must be left floating. Connection of these leads may impair performance or cause damage to the device.
Note: I = Input; O = Output; P = Power; T=Tristate
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QE1M TXC-04252
A DROP AND A ADD BUS I/O Symbol 160-Lead PQFP Lead No. 26
DATA SHEET
208-Lead I/O/P Type * PBGA Lead No. K3 I TTL
Name/Function
ADCLK
A Drop Bus Clock: This clock operates at 19.44 MHz for STM-1/STS-3 operation, and at 6.48 MHz for STS-1 operation. A Drop bus byte-wide data (AD7-AD0), the parity bit (ADPAR), SPE indication (ADSPE), and the C1J1V1 indication (ADC1J1V1) are clocked in on falling edges of this clock. This clock may also be used for timing and deriving the like-named add bus byte-wide data, add and TU/VT indications, and parity bits. The add bus signals are clocked out on rising edges of the clock during the time slots that correspond to the selected TU/VT. A Drop Bus Parity Bit: An odd parity bit input signal representing the parity calculation for each data byte, SPE, and C1J1V1 signal from the drop bus. Control bits are provided in address 012H which enable parity to be calculated as even (control bit DPE is 1), and/or for the data byte only (control bit PDDO is 1). A Drop Bus Data Byte: Byte-wide data that corresponds to the STM-1/STS-3/STS-1 signal from the drop bus. The first bit received (dropped) corresponds to bit 7. A Drop Bus SPE Indicator: A signal that is active high during each byte of the STM-1/STS-3/STS-1 payload, and low during Transport Overhead times. A Drop Bus C1J1V1 Indications: An active high timing signal that carries STM-1/STS-3/STS-1 starting frame and SPE information. This signal works in conjunction with the ADSPE signal. The C1 pulse identifies the location of the first C1 byte in the STM-1/STS-3 signal, and the C1 byte in the STS-1 signal, when ADSPE is low. The J1 signal identifies the starting location of the J1 signal when ADSPE is high. One or more V1 pulses may be present depending upon the format. The V1 pulses may be used in place of the H4 byte as the multiframe indication.
ADPAR
42
T3
I
TTL
AD(7-0)
43, 44, 46-48, 50-52 33
R4, P4, T5, P5, N5, T6, P6, N6 M3
I
TTL
ADSPE
I
TTL
ADC1J1V1
32
L2
I
TTL
ADIND
24
J2
O
CMOS A Drop Bus TU/VT Selection Indication: Enabled when 4mA control bit ADnEN is written with a 1. An active low signal that is clocked out for the time slots determined by TU/VT selection (RTUNn register) for each port (n=port number, 1-4).
*See Input, Output and Input/Output Parameters section below for Type definitions.
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DATA SHEET
QE1M TXC-04252
Symbol
160-Lead PQFP Lead No. 28
208-Lead I/O/P Type * PBGA Lead No. K2 I TTL
Name/Function
AACLK
A Add Bus Clock: When the add bus timing mode is selected, this input must be provided for add bus timing. This clock operates at 19.44 MHz for STM-1/STS-3 operation, and at 6.48 MHz for STS-1 operation. The add bus SPE indication (AASPE), and the C1J1V1 indication (AAC1J1V1) are clocked in on falling edges of this clock. Add bus byte-wide data (AA7-AA0), add indicator (AADD), and parity bit (AAPAR) are clocked out on rising edges of the clock during the time slots that correspond to the selected TU/VT. When drop bus timing is selected, this input is disabled.
AAPAR
55
T7
O(T) CMOS A Add Bus Parity Bit: An odd parity output signal that is 4mA calculated over the byte-wide add data. This tristate lead is only active when there is data being added to the add bus. When control bit APE is 1, even parity is calculated. O(T) CMOS A Add Bus Data Byte: Byte-wide data that corresponds to 4mA the selected TU/VT.
AA(7-0)
56, 58, 59, 60, 62, 63, 64, 65 31
P7, P8, N8, N9, R9, N10, P10, T10 L1
AASPE
I
TTL
A Add Bus SPE Indicator: When the add bus timing mode is selected, this signal must be provided for add bus timing. This signal must be high during each byte of the STM-1/STS-3/STS-1 payload, and low during Transport Overhead byte times. A Add Bus C1J1V1 Indications: When the add bus timing mode is selected, this signal must be provided for add bus timing. An active high timing signal that carries STM-1/STS-3/STS-1 starting frame and SPE information. This signal works in conjunction with the AASPE signal. The C1 pulse identifies the location of the first C1 byte in the STM-1/STS-3 signal, and the C1 byte in the STS-1 signal, when AASPE is low. The J1 signal identifies the starting location of the J1 signal when AASPE is high. The J1 signal identifies the location of the J1 byte. One or more V1 pulses may be present depending upon the format. The V1 pulses are used in place of the H4 byte as the multiframe indication.
AAC1J1V1
30
L4
I
TTL
AAIND
23
J3
O
CMOS A Add Bus TU/VT Selection Indication: Enabled when 4mA control bit AAnEN is written with a 1. An active low signal that is clocked out for the time slots determined by TU/VT selection (TTUNn register) for each port (n=port number, 1-4). CMOS A Add Bus Add Data Present Indicator: This normally 4mA active low signal is present when output data to the A Add bus is valid. It identifies the location of all of the TU/VT time slots being selected. When control bit ADDI is 1, the indicator is active high instead of active low.
AADD
54
R7
O
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QE1M TXC-04252
B DROP AND B ADD BUS I/O Symbol 160-Lead 208-Lead PBGA PQFP Lead No. Lead No. 99 K14
DATA SHEET
I/O/P
Type
Name/Function
BDCLK
I
TTL
B Drop Bus Clock: This clock operates at 19.44 MHz for STM-1/STS-3 operation, and at 6.48 MHz for STS-1 operation. B Drop bus byte-wide data (BD7-BD0), the parity bit (BDPAR), SPE indication (BDSPE), and the C1J1V1 indication (BDC1J1V1) are clocked in on falling edges of this clock. This clock may also be used for timing and deriving the like-named add bus byte-wide data, add and TU/VT indications, and parity bits. The add bus signals are clocked out on rising edges of the clock during the time slots that correspond to the selected TU/VT. B Drop Bus Parity Bit: An odd parity bit input signal representing the parity calculation for each data byte, SPE, and C1J1V1 signal from the drop bus. Control bits are provided in address 012H which enable parity to be calculated as even (control bit DPE is 1), and/or for the data byte only (control bit PDDO is 1). B Drop Bus Data Byte: Byte-wide data that corresponds to the STM-1/STS-3/STS-1 signal from the drop bus. The first bit received (dropped) corresponds to bit 7. B Drop Bus SPE Indicator: A signal that is active high during each byte of the STM-1/STS-3/STS-1 payload, and low during Transport Overhead times. B Drop Bus C1J1V1 Indications: An active high timing signal that carries STM-1/STS-3/STS-1 starting frame and SPE information. This signal works in conjunction with the BDSPE signal. The C1 pulse identifies the location of the first C1 byte in the STM-1/STS-3 signal, and the C1 byte in the STS-1 signal, when BDSPE is low. The J1 signal identifies the starting location of the J1 signal when BDSPE is high. One or more V1 pulses may be present depending upon the format. The V1 pulses may be used in place of the H4 byte as the multiframe indication.
BDPAR
91
M14
I
TTL
BD(7-0)
90-87, 85-82
M16, M15, N13, N16, P16, P15, R16, P14 L15
I
TTL
BDSPE
93
I
TTL
BDC1J1V1
94
L16
I
TTL
BDIND
101
J14
O
CMOS B Drop Bus TU/VT Selection Indication: Enabled when 4mA control bit BDnEN is written with a 1. An active low signal that is clocked out for the time slots determined by TU/VT selection (RTUNn register) for each port (n=port number, 1-4).
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DATA SHEET
QE1M TXC-04252
Symbol
160-Lead 208-Lead PBGA PQFP Lead No. Lead No. 98 K16
I/O/P
Type
Name/Function
BACLK
I
TTL
B Add Bus Clock: When the add bus timing mode is selected, this input must be provided for add bus timing. This clock operates at 19.44 MHz for STM-1/STS-3 operation, and at 6.48 MHz for STS-1 operation. The add bus SPE indication (BASPE), and the C1J1V1 indication (BAC1J1V1) are clocked in on falling edges of this clock. Add bus byte-wide data (BA7-BA0), add indicator (BADD), and parity bit (BAPAR) are clocked out on rising edges of the clock during the time slots that correspond to the selected TU/VT. When drop bus timing is selected, this input is disabled.
BAPAR
77
T14
O(T) CMOS B Add Bus Parity Bit: An odd parity output signal that is 4mA calculated over the byte-wide add data. This tristate lead is only active when there is data being added to the add bus. When control bit APE is 1, even parity is calculated. O(T) CMOS B Add Bus Data Byte: Byte-wide data that corresponds to 4mA the selected TU/VT.
BA(7-0)
76, 75, 73, T13, R13, 72, 71, 69, R12, T12, 68, 67 P12, T11, P11, N11 95 L14
BASPE
I
TTL
B Add Bus SPE Indicator: When the add bus timing mode is selected, this signal must be provided for add bus timing. This signal must be high during each byte of the STM-1/STS-3/STS-1 payload, and low during Transport Overhead byte times. B Add Bus C1J1V1 Indications: When the add bus timing mode is selected, this signal must be provided for add bus timing. An active high timing signal that carries STM-1/STS-3/STS-1 starting frame and SPE information. This signal works in conjunction with the BASPE signal. The C1 pulse identifies the location of the first C1 byte in the STM-1/STS-3 signal, and the C1 byte in the STS-1 signal, when BASPE is low. The J1 signal identifies the starting location of the J1 signal when BASPE is high. The J1 signal identifies the location of the J1 byte. One or more V1 pulses may be present depending upon the format. The V1 pulses are used in place of the H4 byte as the multiframe indication.
BAC1J1V1
96
L13
I
TTL
BAIND
102
J13
O
CMOS B Add Bus TU/VT Selection Indication: Enabled when 4mA control bit BAnEN is written with a 1. An active low signal that is clocked out for the time slots determined by TU/VT selection (TTUNn register) for each port (n=port number, 1-4). CMOS B Add Bus Add Data Present Indicator: This normally 4mA active low signal is present when output data to the B Add bus is valid. It identifies the location of all of the TU/VT time slots being selected. When control bit ADDI is 1, the indicator is active high instead of active low.
BADD
78
R14
O
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QE1M TXC-04252
DATA SHEET
PORT n LINE INTERFACE (n = 1, 2, 3 or 4) Symbol 160-Lead 208-Lead PBGA PQFP Lead No. Lead No. 14, 111, 10, 114 F1, E13, E1, D14 I/O/P Type Name/Function
RCOn (n=1-4)
O(T)
CMOS Receive Port n Output Clock: A 2.048 MHz clock out4mA put. Data is normally clocked out on rising edges of this clock. When control bit RCKI is 1, data is clocked out on falling edges of this clock. When control bit RnEN is 0, this lead is forced to a high impedance state. CMOS Receive Port n Data Positive Rail or NRZ: When con4mA trol bit BYPASn is 0, positive rail data is provided on this lead. When control bit BYPASn is 1, an NRZ signal is provided on this lead. When control bit RnEN is 0, this lead is forced to a high impedance state. CMOS Receive Port n Data Negative Rail: When control bit 4mA BYPASn is 0, negative rail data is provided on this lead. When control bit RnEN is 0, or control bit BYPASn is 1, this lead is forced to a high impedance state. TTL Transmit Port n Input Clock: A 2.048 MHz clock input. Data is normally clocked in on falling edges of this clock. When control bit TCKI is 1, data is clocked in on the rising edges of this clock. Transmit Port n Data Positive Rail or NRZ: When control bit BYPASn is 0, positive rail input data is provided on this lead. When control bit BYPASn is 1, an NRZ signal is provided on this lead. Transmit Port n Data Negative Rail/External Loss Of Signal: When control bit BYPASn is 0, negative rail input data is provided on this lead. When control bit BYPASn is 1, this lead may be used to input an active low external loss of signal indicator from the line interface device. Quiet Port n: A high forces the RPOn and RNOn leads to the 0 state for either a rail or NRZ interface, overriding control bit RnEN when it is 0. A low disables this feature.
RPOn (n=1-4)
16, 109, 12, 112
F4, F14, E4, E14
O(T)
RNOn (n=1-4)
15, 110, 11, 113
F3, F16, E3, E15
O(T)
TCIn (n=1-4)
19, 106, 6, 118
G1, G14, D3, A16
I
TPIn (n=1-4)
21, 104, 8, 116
H1, H15, D4, C16
I
TTL
TNIn/ TLOSn (n=1-4) QUIETn (n=1-4)
20, 105, 7, 117
G4, G13, D1, C15
I
TTL
18, 107, 5, 119
G2, G16, D2, B15
I
TTL
MICROPROCESSOR BUS INTERFACE SELECTION Symbol 160-Lead 208-Lead PQFP PBGA Lead No. Lead No. MUX 3 C1 I/O/P Type Name/Function
I
TTL
Multiplex Mode: A high placed on this lead configures the microprocessor bus to a multiplexed address/data bus interface. A low configures the Intel or Motorola interfaces (see Symbol MOTO below).
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DATA SHEET
QE1M TXC-04252
Symbol 160-Lead 208-Lead PQFP PBGA Lead No. Lead No. MOTO 2 B1
I/O/P
Type
Name/Function
I
TTL
Motorola Mode: Enabled when a low is placed on the MUX lead. The following table lists the bus selection options. MUX H L L MOTO L or H L H Action Multiplex bus interface Intel bus interface Motorola bus interface
This selection modifies some bus interface lead functions, as described in the next two sections of this table.
MICROPROCESSOR BUS INTERFACE - MULTIPLEXED BUS Symbol 160-Lead PQFP Lead No. 1, 160, 159 208-Lead PBGA Lead No. C3, B2, A2 I/O/P Type Name/Function
UPA(10-8)
I (Note 1)
Address Bus: These are additional address lines TTL (Note 1) for accessing QE1M memory locations (most significant three bits). UPA10 is the most significant bit. High is logic 1. TTL 8mA Address/Data Bus: These leads are the time-multiplexed address (lower eight bits only) and data bus for accessing the QE1M memory locations. UPAD7 is the most significant bit. High is logic 1. Select: An active low signal generated by the microprocessor for accessing the QE1M memory locations. Read: An active low signal generated by the microprocessor for reading the QE1M memory locations. The memory map is selected by placing a low on the select lead. Write: An active low signal generated by the microprocessor for writing to QE1M memory locations. The memory map is selected by placing a low on the select lead. Address Latch Enable: An active high signal generated by the microprocessor for holding an address stable during a read or write cycle. Ready: A high is an acknowledgment from the addressed memory location that the transfer can be completed. A low indicates that the Mapper cannot complete the transfer cycle, and that microprocessor wait states must be generated. Interrupt: A high or low on this output lead signals an interrupt request to the microprocessor. The polarity of this signal is determined by the state of the INTSH lead.
UPAD(7-0) 133, 132, 130, 129, 128, 126, 125, 124 SEL 146
D11, C11, C12, A12, B12, A13, C13, B13 B8
I/O
I
TTL
RD
147
D7
I
TTL
WR
148
C7
I
TTL
ALE
149
A7
I
TTL
RDY
122
A15
O(T)
TTL 8mA
INT
152
D6
O(T)
TTL 8mA
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QE1M TXC-04252
DATA SHEET
Symbol
160-Lead PQFP Lead No. 150
208-Lead PBGA Lead No. B7
I/O/P
Type
Name/Function
INTSH
I
TTL
Interrupt Sense High Selection: A high on this lead causes the interrupt sense to be high when an interrupt occurs. A low causes the interrupt sense to be low when an interrupt occurs.
Note 1: Leads UPA(10-8) are implemented as Input/Output type TTL 4mA to support production tests but are used as TTL inputs.
MICROPROCESSOR BUS INTERFACE - SPLIT BUS FOR MOTOROLA (M) OR INTEL (I) Symbol 160-Lead 208-Lead PQFP PBGA Lead No. Lead No. A(10-0) 1, 160, 159, 158, 156, 153, 144, 143, 141, 140, 135 C3, B2, A2, A3, B5, C6, C8, D8, C9, B9, B10 I/O/P Type Name/Function
I TTL Address Bus (Motorola/Intel Buses): These address (Note 1) (Note 1) line inputs are used for accessing a QE1M memory location for a read/write cycle. A10 is the most significant bit. High is logic 1.
D(7-0)
133, 132, D11, C11, 130, 129, C12, A12, 128, 126, B12, A13, 125, 124 C13, B13 146 B8
I/O
TTL 8mA
Data Bus (Motorola/Intel Buses): Bidirectional data lines used for transferring data to or from a QE1M memory location. D7 is the most significant bit. High is logic 1. Select: A low enables data transfers between the microprocessor and the QE1M memory during a read/write cycle. Read (I mode) or Read/Write (M mode): Intel Mode - An active low signal generated by the microprocessor for reading the QE1M memory locations. Motorola Mode - An active high signal generated by the microprocessor for reading the QE1M memory locations. An active low signal is used to write to memory locations. Write (I mode) or Device Select (M mode): Intel Mode - An active low signal generated by the microprocessor for writing to the QE1M memory locations. Motorola Mode - The SEL and LDS inputs are logically OR-gated inside the QE1M, generating an internal active low select signal (CS) that is similar to SEL. This internal signal is used to enable data transfer. This lead can be used for the interface with the Motorola 68302 microprocessor. If it is not used, it should be tied to ground, so that CS is the same signal as SEL.
SEL
I
TTL
RD / RD/WR
147
D7
I
TTL
WR / LDS
148
C7
I
TTL
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DATA SHEET
QE1M TXC-04252
Symbol 160-Lead 208-Lead PBGA PQFP Lead No. Lead No. RDY / DTACK 122 A15
I/O/P
Type
Name/Function
O(T)
TTL 8mA
Ready (I mode) or Data Transfer Acknowledge (M mode): Intel Mode - A high is an acknowledgment from the addressed QE1M memory location that the transfer can be completed. A low indicates that the Mapper cannot complete the transfer cycle, and that microprocessor wait states must be generated. Motorola Mode - During a read bus cycle, a low signal indicates that the information on the data bus is valid. During a write bus cycle, a low signal acknowledges the acceptance of data. This lead is tristated. Interrupt: When INTSH is high, a high on this output lead signals an interrupt request INT to the microprocessor, as required for Intel. When INTSH is low, a low signals an interrupt request IRQ to the microprocessor, as required for Motorola. Interrupt Sense High: Interrupt polarity select. A high on this lead causes the interrupt sense to be high when an interrupt occurs. A low causes the interrupt sense to be low when an interrupt occurs. This lead must be set to meet the interrupt polarity requirement of the microprocessor.
INT/ IRQ
152
D6
O(T)
TTL 8mA
INTSH
150
B7
I
TTL
Note 1: Leads A(10-0) are implemented as type Input/Output type TTL 4mA to support production tests but are used as TTL inputs.
CONTROLS, EXTERNAL CLOCK AND TEST LEADS Symbol 160-Lead 208-Lead PQFP PBGA Lead No. Lead No. TEST TEST 121 145 C14 A8 I/O/P Type Name/Function
I I
CMOS TranSwitch Test Lead: A low must be placed on this lead. TTLp TranSwitch Test Lead: This lead is pulled high internally by an internal pull-up to VDD. It must be left floating or held high.
EXTCK
138
D10
I
CMOS External Reference Clock: This clock is used for desynchronizer operation and other purposes. The clock frequency must be 58.32 MHz (+/- 30 ppm over life) and the clock duty cycle must be (50 +/- 10) %. TTL Hardware Reset: When an active low pulse is applied to this lead for a minimum duration of 150 nanoseconds after power is applied, this pulse clears all performance counters and alarms, resets the control bits (except those bits that force a high impedance state for the add buses), and initializes the internal FIFOs and internal SPOT processor. The microprocessor must write the control bit states for normal operation.
RESET
155
C5
I
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QE1M TXC-04252
DATA SHEET
Symbol 160-Lead 208-Lead PQFP PBGA Lead No. Lead No. HIGHZ 136 A10
I/O/P
Type
Name/Function
I
TTL
High Impedance Select: A low forces all output leads to the high impedance state for testing purposes (except TDO). Add Bus Timing Select: A low selects the A and B Add bus clock, SPE and C1J1V1 input signals for deriving timing for the A and B Add buses. A high selects the like-named drop bus for deriving timing (e.g., A Drop bus for A Add bus). This control lead is disabled when a 1 is written to control bit SBTEN.
ABUST
157
A4
I
TTL
BOUNDARY SCAN INTERFACE SIGNALS Symbol 160-Lead 208-Lead PQFP PBGA Lead No. Lead No. 39 R2 I/O/P Type Name/Function
TCK
I
TTL
IEEE 1149.1 Test Port Serial Scan Clock: This signal is used to shift data into TDI on the rising edge, and out of TDO on the falling edge. The maximum clock frequency is 10 MHz. IEEE 1149.1 Test Port Mode Select: TMS is sampled on the rising edge of TCK, and is used to place the Test Access Port controller into various states as defined in IEEE 1149.1. This lead is set high internally by an internal pull-up to VDD for normal framer operation. IEEE 1149.1 Test Port Serial Scan Data In: Serial test instructions and data are clocked into this lead on the rising edge of TCK. This input has an internal pull-up to VDD. IEEE 1149.1 Test Port Serial Scan Data Out: Serial test instructions and data are clocked out of this lead on the falling edge of TCK. When inactive, this 3-state output will be put into its high impedance state. IEEE 1149.1 Test Port Reset Lead: This lead will asynchronously reset the Test Access Port (TAP) controller. This lead is to be held low, asserted low or pulsed low (for a minimum duration of 20 ns) to reset the TAP controller on QE1M power-up. This input has an internal pull-up to VDD.
TMS
36
N2
I
TTLp
TDI
38
R1
I
TTLp
TDO
37
P1
O(T)
TTL 4mA
TRS
35
N1
I
TTLp
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DATA SHEET ABSOLUTE MAXIMUM RATINGS AND ENVIRONMENTAL LIMITATIONS
Parameter Supply voltage DC input voltage Storage temperature range Ambient Operating Temperature Moisture Exposure Level Relative Humidity, during assembly Relative Humidity, in-circuit ESD Classification Latch-up Symbol VDD VIN TS TA ME RH RH ESD LU Min -0.5 -0.5 -55 -40 5 30 0 60 100 Max +6.0 VDD + 0.5 150 85 Unit V V
oC oC
QE1M TXC-04252
Conditions Note 1 Note 1 Note 1 0 ft/min linear airflow per EIA/JEDEC JESD22-A112-A Note 2 non-condensing Note 3 JEDEC STD-17
Level % % V
Absolute value 2000
Notes: 1. Conditions exceeding the Min or Max values may cause permanent failure. Exposure to conditions near the Min or Max values for extended periods may impair device reliability. 2. Pre-assembly storage in non-drypack conditions is not recommended. Please refer to the instructions on the "CAUTION" label on the drypack bag in which devices are supplied. 3. Absolute value tested per MIL-STD-883D, Method 3015.7.
THERMAL CHARACTERISTICS
The thermal characteristics of the PQFP and PBGA versions of the QE1M device are shown in the table below: Parameter Thermal resistance: junction to ambient for PQFP Thermal resistance: junction to ambient for PBGA Min --Typ --Max 41.4 38 Unit
o
Test Conditions 0 ft/min linear airflow 0 ft/min linear airflow
C/W
oC/W
POWER REQUIREMENTS
Parameter VDD IDD Power dissipation, PDD IDD Power dissipation, PDD Min 4.75 Typ 5.0 110 550 136 680 Max 5.25 143 750 170 900 Unit V mA mW mA mW STS-1 STS-1 STM-1 or STS-3 STM-1 or STS-3 Test Conditions
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QE1M TXC-04252
DATA SHEET
INPUT, OUTPUT AND INPUT/OUTPUT PARAMETERS
INPUT PARAMETERS Input Parameters For CMOS Parameter VIH VIL Input capacitance 7.5 Min 0.7 * VDD 0.3 * VDD Typ Max Unit V V pF Test Conditions 4.75 VDD 5.25 4.75 VDD 5.25
Input Parameters For TTL Parameter VIH VIL Input capacitance 7.5 Min 2.0 0.8 Typ Max Unit V V pF Test Conditions 4.75 VDD 5.25 4.75 VDD 5.25
Input Parameters For TTLp Parameter VIH VIL Input capacitance Input Resistance 7.5 70 Min 2.0 0.8 Typ Max Unit V V pF k Test Conditions 4.75 VDD 5.25 4.75 VDD 5.25
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DATA SHEET
OUTPUT PARAMETERS
QE1M TXC-04252
Output Parameters For CMOS 4mA Parameter VOH VOL IOL IOH Input capacitance 7.5 Min VDD - 0.7 0.4 4.0 -4.0 Typ Max Unit V V mA mA pF Test Conditions VDD = 4.75; IOH = -4.0 VDD = 4.75; IOL = 4.0
Output Parameters For TTL 4mA Parameter VOH VOL IOL IOH Input capacitance 7.5 Min 2.4 0.4 4.0 -4.0 Typ Max Unit V V mA mA pF Test Conditions VDD = 4.75; IOH = -4.0 VDD = 4.75; IOL = 4.0
Output Parameters For TTL 8mA Parameter VOH VOL IOL IOH Input capacitance 7.5 Min 2.4 0.4 8.0 -8.0 Typ Max Unit V V mA mA pF Test Conditions VDD = 4.75; IOH = -8.0 VDD = 4.75; IOL = 8.0
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QE1M TXC-04252
INPUT/OUTPUT PARAMETERS
DATA SHEET
Input/output Parameters For TTL 4mA Parameter VIH VIL Input capacitance VOH VOL IOL IOH Input capacitance 7.5 2.4 0.4 4.0 -4.0 5.5 Min 2.0 0.8 Typ Max Unit V V pF V V mA mA pF VDD = 4.75; IOH = -4.0 VDD = 4.75; IOL = 4.0 Test Conditions 4.75 VDD 5.25 4.75 VDD 5.25
Input/output Parameters For TTL 8mA Parameter VIH VIL VOH VOL IOL IOH Input capacitance 7.5 2.4 0.4 8.0 -8.0 Min 2.0 0.8 Typ Max Unit V V V V mA mA pF Test Conditions 4.75 VDD 5.25 4.75 VDD 5.25 VDD = 4.75; IOH = -8.0 VDD = 4.75; IOL = 8.0
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DATA SHEET TIMING CHARACTERISTICS
QE1M TXC-04252
Detailed timing diagrams for the QE1M device are illustrated in Figures 5 through 17, with values of the timing intervals tabulated below the waveform diagrams. The tristate condition of a signal waveform is shown as midway between high and low. The timing parameters are measured at voltage levels of (VIH + VIL)/2 for input signals or (VOH + VOL)/2 for output signals, unless otherwise indicated. Where a waveform diagram describes both A and B bus signals, their symbols are combined in labeling the waveform (e.g., A/BADD for AADD and BADD). Figure 5. Ports 1, 2, 3 and 4 E1 Transmit Timing
tCYC tPWL TCIn (Input) tSU tH TPIn/TNIn (Input) tPWH
Note: n = 1 - 4
Notes: 1. TCIn is shown for TCLKI = 0, where data is clocked in on falling edges. Data is clocked in on rising edges when TCLKI =1. 2. For NRZ operation, TNIn is not used for data input and may instead be used as the input for an external active low loss of signal indication TLOSn. Otherwise, this lead must be held high.
Parameter TCIn Clock period TCIn clock low time TCIn clock high time TPIn/TNIn data setup time before TCIn TPIn/TNIn data hold time after TCIn
Symbol tCYC tPWL tPWH tSU tH
Min
Typ 488.28
Max
Unit ns ns ns ns ns
150 150 10 2.0
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QE1M TXC-04252
DATA SHEET
Figure 6. Ports 1, 2, 3 and 4 E1 Receive Timing
tCYC RCOn (Output) tPWH tPWL
RPOn/RNOn (Output)
Note: n = 1 - 4
tOD
Note: RCOn is shown for RCLKI=0, where data is clocked out on rising edges. Data is clocked out on falling edges when RCLKI=1.
Parameter RCOn clock period RCOn clock low time (RCLKI = 0) RCOn clock high time (RCLKI = 0) RCOn clock low time (RCLKI = 1) RCOn clock high time (RCLKI = 1) RPOn/RNOn data delay after RCOn
Symbol tCYC tPWL tPWH tPWL tPWH tOD
Min 480
Typ
Max 498
Unit ns ns ns ns ns ns
257 222 222 257 2.0 5.0 241 241
Note: All output times are measured with a maximum 75 pF load capacitance.
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QE1M TXC-04252
Figure 7. STS-1 A/B Drop and Add Bus Signals, Timing Derived from Drop Bus
tCYC A/BDCLK (Input) tSU(1) A/BD(7-0) A/BDPAR (Input) A/BDSPE (Input) tSU(3) A/BDC1J1V1 (Input) A/BDIND (Output) A/BA(7-0) A/BAPAR (Output) A/BADD (Output) tOD(4) A/BAIND (Output)
Add Bus TU/VT Time Slot when enabled
tPWH
tH(1) C1 tSU(2) Data tH(2) tH(3) C1 tD(1) tOD(2)
TU/VT Selected Occurs every four frames when provided in place of the H4 byte
A1
A2
Data
TU/VT Selected
J1
Data
Data
J1
V1
Drop Bus TU/VT Time Slot when enabled
tOD(3)
tOD(5) tOD(1)
Note: For illustration purposes, a single TU/VT (TU number 21) is shown. The V1 pulse may or may not be present. If it is not present, the H4 byte must be provided. An additional byte time of delay in A/BA(7-0) is provided when control bit ABD is written with a 1. The table omits A/B parameter prefixes. DSPE edges are at payload boundaries.
Parameter DCLK clock period DLCK duty cycle tPWH/tCYC D(7-0)/DPAR data /parity setup time before DCLK D(7-0)/DPAR data /parity hold time after DCLK DSPE setup time before DCLK DSPE hold time after DCLK DC1J1V1 setup time before DCLK DC1J1V1 hold time after DCLK DIND drop bus indication output delay from DCLK A(7-0)/APAR data /parity out valid delay from DCLK A(7-0)/APAR data /parity to tristate delay from DCLK ADD add indicator delay from DCLK AIND add bus indication output delay from DCLK A(7-0)/APAR data /parity out tristate to driven delay from DCLK
Symbol tCYC
Load
Min 40
Typ 154.32 50
Max 60
Unit ns % ns ns ns ns ns ns
tSU(1) tH(1) tSU(2) tH(2) tSU(3) tH(3) tD(1) tOD(2) tOD(3) tOD(1) tOD(4) tOD(5) 25pF 75pF 25pF 75pF
10 5.0 10 5.0 10 5.0 7.0 9.0 8.0 9.0 9.0 7.0 30 39 20 30 30 9.0
ns ns ns ns ns ns
Note: All output times are measured with the specified load capacitance.
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QE1M TXC-04252
DATA SHEET
Figure 8. STM-1/STS-3 A/B Drop and Add Bus Signals, Timing Derived from Drop Bus
tCYC A/BDCLK (Input) tSU(1) A/BD(7-0) A/BDPAR (Input) A/BDSPE (Input) A/BDC1J1V1 (Input) A/BDIND (Output) A/BA(7-0) APAR (Output) A/BADD (Output) A/BAIND (Output)
tSU(3)
C1(1) C1(1)
tPWH
tH(1)
C1(2) C1(3) Data
TU/VT Selected J1 Byte STS-1 #1
STS-1 #2
STS-1 #3
Data STS-1 #1
tSU(2)
tH(2)
Occurs every four frames when provided in place of the H4 byte J1 STS-1 #1 J1 STS-1 #2 J1 STS-1 #3 V1 STS-1 #1
tH(3)
tD(1) tOD(2)
Drop Bus TU/VT Time Slot selected when enabled
tOD(3)
TU/VT Selected
tOD(5) tOD(1) tOD(4)
Add Bus TU/VT Time Slot selected when enabled
Note: A single TU/VT is shown for illustration purposes. It also shows the TU/VT selection for the drop bus and add bus (number 21 in STS-1 number 3). The format is an AU-3/STS-3. For VC-4 operation, one J1 pulse and one optional V1 pulse are present. An additional byte time of delay in A/BA(7-0) is provided when control bit ABD is written with a 1. The table omits A/B parameter prefixes. DSPE edges are at payload boundaries.
Parameter DCLK clock period DCLK duty cycle tPWH/tCYC D(7-0)/DPAR data /parity setup time before DCLK D(7-0)/DPAR data /parity hold time after DCLK DSPE setup time before DCLK DSPE hold time after DCLK DC1J1V1 setup time before DCLK DC1J1V1 hold time after DCLK DIND drop bus indication output delay from DCLK A(7-0)/APAR data /parity out valid delay from DCLK A(7-0)/APAR data /parity to tristate delay from DCLK ADD add indicator delay from DCLK AIND add bus indication output delay from DCLK A(7-0)/APAR data /parity out tristate to driven delay from DCLK
Symbol tCYC
Load
Min 40
Typ 51.44 50
Max 60
Unit ns % ns ns ns ns ns ns
tSU(1) tH(1) tSU(2) tH(2) tSU(3) tH(3) tD(1) tOD(2) tOD(3) tOD(1) tOD(4) tOD(5) 25pF 75pF 25pF 75pF
10 5.0 10 5.0 10 5.0 7.0 9.0 8.0 9.0 9.0 7.0 30 39 20 30 30 9.0
ns ns ns ns ns ns
Note: All output times are measured with the specified load capacitance.
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DATA SHEET
Figure 9. STS-1 A/B Add Bus Signals, Timing Derived from Add Bus
tCYC A/BACLK (Input) tSU(2) A/BASPE (Input) A/BAC1J1V1 (Input) A/BA(7-0) A/BAPAR (Output) A/BADD (Output) A/BAIND (Output) tSU(1) C1 tOD(2) tOD(5) tOD(1)
TU/VT Selected
QE1M TXC-04252
tPWH
tH(2)
Occurs every four frames when provided
tH(1) J1 V1 tOD(3)
tOD(4)
Add Bus TU/VT Time Slot when enabled
Notes: For illustration purposes, a single TU/VT is shown. The location of this TU/VT corresponds to TU/VT number 21. An additional byte time of delay in A/BA(7-0) is provided when control bit ABD is written with a 1. The table omits A/B parameter prefixes. ASPE edges are at payload boundaries.
Parameter ACLK clock period ACLK duty cycle, tPWH/tCYC AC1J1V1 setup time before ACLK AC1J1V1 hold time after ACLK ASPE setup time before ACLK ASPE hold time after ACLK A(7-0)/APAR data /parity out valid delay from ACLK A(7-0)/APAR data /parity to tristate delay from ACLK ADD add indicator delayed from ACLK AIND add bus indication output delay from ACLK A(7-0)/APAR data /parity out tristate to driven delay from ACLK
Symbol tCYC
Load
Min
Typ 154.32
Max
Unit ns
40 tSU(1) tH(1) tSU(2) tH(2) tOD(2) tOD(3) tOD(1) tOD(4) tOD(5) 75pF 10 5.0 10 5.0 7.0 7.0 7.0 7.0 5.0
50
60
% ns ns ns ns
31 16 24 24 7.0
ns ns ns ns ns
25pF 75pF
Note: All output times are measured with the specified load capacitance.
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QE1M TXC-04252
DATA SHEET
Figure 10. STM-1/STS-3 A/B Add Bus Signals, Timing Derived from Add Bus
tCYC A/BACLK (Input) A/BASPE (Input)
tSU(1) tH(1)
C1(1) J1 STS-1 #1 J1 STS-1 #2 J1 STS-1 #3
tPWH tSU(2)
tH(2)
Occurs every four frames when enabled
A/BAC1J1V1
(Input)
V1 STS-1 #1
V1 STS-1 #2
V1 STS-1 #3
tOD(2) A/BA(7-0) A/BAPAR (Output) A/BADD (Output) A/BAIND (Output)
TU/VT Selected
tOD(3)
tOD(5) tOD(1)
tOD(4)
Add Bus TU/VT Time Slot selected when enabled
Note: A single TU/VT is shown for illustration purposes. It also shows the TU/VT selection for the drop bus and add bus (number 21 in STS-1 number 3). The format is an AU-3/STS-3. For VC-4 operation, one J1 pulse and one optional V1 pulse are present. An additional byte time of delay in A/BA(7-0) is provided when control bit ABD is written with a 1. The table omits A/B parameter prefixes. ASPE edges are at payload boundaries.
Parameter ACLK clock period ACLK duty cycle, tPWH/tCYC AC1J1V1 setup time before ACLK AC1J1V1 hold time after ACLK ASPE setup time before ACLK ASPE hold time after ACLK A(7-0)/APAR data /parity out valid delay from ACLK A(7-0)/APAR data /parity to tristate delay from ACLK ADD add indicator delayed from ACLK AIND add bus indication output delay from ACLK A(7-0)/APAR data /parity out tristate to driven delay from ACLK
Symbol tCYC
Load
Min
Typ 51.44
Max
Unit ns
40 tSU(1) tH(1) tSU(2) tH(2) tOD(2) tOD(3) tOD(1) tOD(4) tOD(5) 75pF 10 5.0 10 5.0 7.0 7.0 7.0 7.0 5.0
50
60
% ns ns ns ns
31 16 31 31 7.0
ns ns ns ns ns
25pF 75pF
Note: All output times are measured with the specified load capacitance.
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Figure 11. Microprocessor Read Cycle Timing - Multiplex Bus
QE1M TXC-04252
tPW(1) ALE (Input) tSU(1) UPA(10-8)* UPAD(7-0) (Input/Output) tH(1) Address tOD(4) tSU(2) SEL (Input) tW(2) RD (Input) tD(1) RDY (Output)
tristate
tW(1)
tH(2) Data
tOD(1)
tOD(2) tOD(3)
tH(3)
tPW(2)
tD(2)
tF(1)
tristate
* Address input only
tPW(3)
Parameter ALE pulse width UPA(10-8) and UPAD(7-0) address setup time before ALE UPA(10-8) and UPAD(7-0) address hold time after ALE UPA(10-8) and UPAD(7-0) address hold time after RD UPAD(7-0) data output delay to tristate after RD ALE wait time after RD SEL setup before RD SEL hold time after RD RD wait after ALE RD pulse width RDY delay after SEL RDY delay after RD RDY float time after SEL
Symbol tPW(1) tSU(1) tH(1) tH(2) tOD(1) tW(1) tSU(2) tH(3) tW(2) tPW(2) tD(1) tD(2) tF(1)
Min 20 5.0 3.0
Typ
Max
Unit ns ns ns
2.0 2.0 0.0 0.0 0.0 20 40 2.0 4.0 2.0 10 20 10 11
ns ns ns ns ns ns ns ns ns ns
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DATA SHEET
Parameter Register cycle RDY pulse width SPOT instruction read (Note 2) Data RAM read (Note 3) UPAD(7-0) data output Register read only delay after RD UPAD(7-0) data output SPOT instruction read and data delay after RDY RAM read only UPAD(7-0) data output tristate to driven delay after RD
Symbol tPW(3)
Min 6 * SPcyc 9 * SPcyc
Typ
Max 0.0 7 * SPcyc 33 * SPcyc 28 0.0
Unit ns ns ns ns ns ns
tOD(2) tOD(3) tOD(4)
8.0
2.0
Notes: 1. All output times are measured with a maximum 75 pF load capacitance. 2. One SPcyc equals two EXTCK clock cycles. (The EXTCK clock frequency is 58.32 MHz. One SPcyc is about 34.29 ns.) 3. Excessive external microprocessor data RAM access could interfere with the QE1M internal data processing, resulting in data corruption. To prevent such a situation, when excessive external microprocessor data RAM access is detected, QE1M tries to slow down the external microprocessor access rate by lengthening the RDY pulse width to as high as 97 * SPcyc.
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DATA SHEET
Figure 12. Microprocessor Write Cycle Timing - Multiplex Bus
QE1M TXC-04252
tPW(1)
ALE (Input) UPA(10-8)* UPAD(7-0) (Input) SEL (Input)
tW(1)
tSU(1)
tH(1) Address tSU(3)
tSU(2) Data tSU(4)
tH(2)
tH(3)
WR (Input)
tW(2)
tPW(2)
tD(2)
RDY (Output)
tF(1)
tD(1) tPW(3)
* Address input only
Parameter ALE pulse width ALE wait after WR UPA(10-8) and UPAD(7-0) address setup time before ALE UPA(10-8) and UPAD(7-0) address hold time after ALE UPAD(7-0) data input setup time before WR UPAD(7-0) data input hold time after WR SEL setup time before WR SEL hold time after WR WR wait after ALE WR pulse width RDY delay after SEL RDY delay after WR RDY float time after SEL
Symbol tPW(1) tW(1) tSU(1) tH(1) tSU(2) tH(2) tSU(3) tH(3) tW(2) tPW(2) tD(1) tD(2) tF(1)
Min 20 0.0 5.0 3.0 12 6.0 0.0 0.0 20 40 2.0 4.0 2.0
Typ
Max
Unit ns ns ns ns ns ns ns ns ns ns
10 20 10
ns ns ns
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DATA SHEET
Parameter Register write RDY pulse width SPOT instruction write (Note 2) Data RAM write (Note 3) Data valid set up time SPOT instruction write and data RAM write only to WR
Symbol tPW(3)
Min 5 * SPcyc 9 * SPcyc
Typ
Max 0.0 7 * SPcyc 29 * SPcyc
Unit ns ns ns ns
tSU(4)
-1 * SPcyc
Notes: 1. All output times are measured with a maximum 75 pF load capacitance. 2. One SPcyc equals two EXTCK clock cycles. (The EXTCK clock frequency is 58.32 MHz. One SPcyc is about 34.29 ns.) 3. Excessive external microprocessor data RAM access could interfere with the QE1M internal data processing, resulting in data corruption. To prevent such a situation, when excessive external microprocessor data RAM access is detected, QE1M tries to slow down the external microprocessor access rate by lengthening the RDY pulse width to as high as 97 * SPcyc.
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Figure 13. Microprocessor Read Cycle Timing - Intel
QE1M TXC-04252
tH(1)
A(10-0) (Input)
Address
tD(5)
D(7-0) (Output)
Data tF(1) tSU(1) tD(1)
SEL (Input)
tSU(2)
RD (Input)
tH(2) tPW(1) tD(3)
tD(2)
RDY (Output)
tD(4)
tF(2)
tPW(2)
Parameter A(10-0) address setup time to SEL A(10-0) address hold time after RD D(7-0) data output float time after RD SEL setup time to RD RD pulse width SEL hold time after RD RDY delay after SEL RDY delay after RD RDY float time after SEL
Symbol tSU(1) tH(1) tF(1) tSU(2) tPW(1) tH(2) tD(2) tD(3) tF(2)
Min 0.0 3.0 2.0 10 40 0.0 2.0 4.0 2.0
Typ
Max
Unit ns ns
11
ns ns ns ns
10 20 10
ns ns ns
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DATA SHEET
Parameter Register read RDY pulse width SPOT instruction read (Note 2) Data RAM read (Note 3) Data output valid delay Register read only after RD Data output valid delay SPOT instruction read and data after RDY RAM read only Data output tristate to driven delay after RD
Symbol tPW(2)
Min
Typ
Max 0.0
Unit ns ns ns ns ns ns
6 * SPcyc 9 * SPcyc tD(1) tD(4) tD(5) 2.0 8.0
7 * SPcyc 33 * SPcyc 28 0.0
Notes: 1. All output times are measured with a maximum 75 pF load capacitance. 2. One SPcyc equals two EXTCK clock cycles. (The EXTCK clock frequency is 58.32 MHz. One SPcyc is about 34.29 ns.) 3. Excessive external microprocessor data RAM access could interfere with the QE1M internal data processing, resulting in data corruption. To prevent such a situation, when excessive external microprocessor data RAM access is detected, QE1M tries to slow down the external microprocessor access rate by lengthening the RDY pulse width to as high as 97 * SPcyc.
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DATA SHEET
Figure 14. Microprocessor Write Cycle Timing - Intel
tH(1) A(10-0) (Input) Address tH(2) D(7-0) (Input) tSU(1) SEL (Input) tSU(3) WR (Input) tD(1) RDY (Output) tPW(2) tPW(1) Data tSU(2) tSU(4)
QE1M TXC-04252
tD(2)
tF
Parameter A(10-0) address setup time to SEL A(10-0) address hold time after WR D(7-0) data input valid setup time to WR D(7-0) data input hold time after WR SEL setup time to WR WR pulse width RDY delay after SEL RDY delay after WR RDY float time after SEL Register write RDY pulse width SPOT instruction write (Note 2) Data RAM write (Note 3) D(7-0) data valid setup SPOT instruction write and data time to WR RAM write only
Symbol tSU(1) tH(1) tSU(2) tH(2) tSU(3) tPW(1) tD(1) tD(2) tF tPW(2)
Min 0.0 3.0 12 6.0 10 40 2.0 4.0 2.0 5 * SPcyc 9 * SPcyc
Typ
Max
Unit ns ns ns ns ns ns
10 20 10 0.0 7 * SPcyc 29 * SPcyc
ns ns ns ns ns ns ns
tSU(4)
-1 * SPcyc
Notes: 1. All output times are measured with a maximum 75 pF load capacitance. 2. One SPcyc equals two EXTCK clock cycles. (The EXTCK clock frequency is 58.32 MHz. One SPcyc is about 34.29 ns.) 3. Excessive external microprocessor data RAM access could interfere with the QE1M internal data processing, resulting in data corruption. To prevent such a situation, when excessive external microprocessor data RAM access is detected, QE1M tries to slow down the external microprocessor access rate by lengthening the RDY pulse width to as high as 97 * SPcyc.
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QE1M TXC-04252
DATA SHEET
Figure 15. Microprocessor Read Cycle Timing - Motorola tH(1) RD/WR (Input) A(10-0) (Input) Address tD(1) D(7-0) (Output) tSU(1) CS (Internal) SEL (Input) tPW(3) tD(2) DTACK (Output) tD(3) tD(4) tF(2) tD(5) Data tPW(1) tF(1)
Note: CS is an internal signal which is the logical OR of the SEL and LDS lead input signals. Its timing parameters refer to whichever of these signals controls the associated transition.
Parameter A(10-0) address setup time and RD/WR setup time before CS A(10-0) address hold time and RD/WR delay time after CS D(7-0) data output float time after CS CS pulse width DTACK driven delay after SEL DTACK float time after SEL DTACK stable delay after address becomes stable (Note 4) Register read DTACK pulse width D(7-0) data output delay after CS D(7-0) data output delay after DTACK SPOT instruction read (Note 2) Data RAM read (Note 3) Register read only SPOT instruction read and data RAM read only
Symbol tSU(1) tH(1) tF(1) tPW(1) tD(2) tF(2) tD(3) tPW(3)
Min 10 3.0 2.0 40 2.0 2.0 6.0 6 x SPcyc 9 x SPcyc
Typ
Max
Unit ns ns
11 10 10 26 0.0 7 x SPcyc 33 x SPcyc 28 0.0
ns ns ns ns ns ns ns ns ns ns ns
tD(1) tD(4) tD(5)
8.0
D(7-0) data output tristate to drive delay after CS
2.0
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QE1M TXC-04252
Notes: 1. All output times are measured with a maximum 75 pF load capacitance. 2. One SPcyc equals two EXTCK clock cycles. (The EXTCK clock frequency is 58.32 MHz. One SPcyc is about 34.29 ns.) 3. Excessive external microprocessor data RAM access could interfere with the QE1M internal data processing, resulting in data corruption. To prevent such a situation, when excessive external microprocessor data RAM access is detected, QE1M tries to slow down the external microprocessor access rate by lengthening the DTACK pulse width to as high as 97 x SPcyc. To avoid such delays the following are TranSwitch recommendations for access frequency for the QE1M SPOT data RAM (addresses are shaded in the memory map at the end of the data sheet). a. Use 16 wait states for a read or write access if the DTACK signal is not being used. Forcing a longer wait state for every access may create unwanted delays in the internal process for the QE1M. Using the 16 wait states will provide reliability without causing excessive process delays (at the 25 MHz microprocessor frequency). For other frequencies, use an equivalent number of wait states that equals approximately 640 ns. b. Maintain no more than 16 microprocessor accesses per 125 s frame period. c. Maintain a minimum of 600 ns between microprocessor accesses. 4. During a SPOT instruction read or data RAM read cycle, DTACK stays high after tD(3). During a register read cycle, DTACK settles to low after tD(3). DTACK may go directly from a low to a high impedance state.
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QE1M TXC-04252
DATA SHEET
Figure 16. Microprocessor Write Cycle Timing - Motorola tH(1) RD/WR (Input) A(10-0) (Input) D(7-0) (Input) tSU(3) tSU(1) CS (Internal) SEL (Input) tPW(3) DTACK (Output) tD(2) tD(3) tF tPW(1) Address tSU(2) Data tH(2)
Note: CS is an internal signal which is the logical OR of the SEL and LDS lead input signals. Its timing parameters refer to whichever of those signals controls the associated transition.
Parameter A(10-0) address setup time and RD/WR setup time before CS A(10-0) address hold time and RD/WR delay time after CS D(7-0) data input setup time before CS D(7-0) data input hold time after CS CS pulse width DTACK driven delay after SEL DTACK float time after SEL DTACK stable delay after address becomes stable (Note 4) Register write DTACK pulse width SPOT instruction write (Note 2) Data RAM write (Note 3) D(7-0) data valid setup SPOT instruction write and data time to CS RAM write only
Symbol tSU(1) tH(1) tSU(2) tH(2) tPW(1) tD(2) tF tD(3) tPW(3)
Min 10 3.0 12 6.0 40 2.0 2.0 6.0
Typ
Max
Unit ns ns ns ns ns
10 10 26 0.0
ns ns ns ns ns ns ns
5 x SPcyc 9 x SPcyc tSU(3) -1 x SPcyc
7 x SPcyc 29 x SPcyc
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DATA SHEET
QE1M TXC-04252
Notes: 1. All output times are measured with a maximum 75 pF load capacitance. 2. One SPcyc equals two EXTCK clock cycles. (The EXTCK clock frequency is 58.32 MHz. One SPcyc is about 34.29 ns.) 3. Excessive external microprocessor data RAM access could interfere with the QE1M internal data processing, resulting in data corruption. To prevent such a situation, when excessive external microprocessor data RAM access is detected, QE1M tries to slow down the external microprocessor access rate by lengthening the DTACK pulse width to as high as 97 x SPcyc. To avoid such delays the following are TranSwitch recommendations for access frequency for the QE1M SPOT data RAM (addresses are shaded in the memory map at the end of the data sheet). a. Use 16 wait states for a read or write access if the DTACK signal is not being used. Forcing a longer wait state for every access may create unwanted delays in the internal process for the QE1M. Using the 16 wait states will provide reliability without causing excessive process delays (at the 25 MHz microprocessor frequency). For other frequencies, use an equivalent number of wait states that equals approximately 640 ns. b. Maintain no more than 16 microprocessor accesses per 125 s frame period. c. Maintain a minimum of 600 ns between microprocessor accesses. 4. During a SPOT instruction write or data RAM write cycle, DTACK stays high after tD(3). During a register write cycle, DTACK settles to low after tD(3). DTACK may go directly from a low to a high impedance state.
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QE1M TXC-04252
DATA SHEET
Figure 17. Boundary Scan Timing
tPWL tPWH TCK (INPUT) tH(1) TMS (INPUT) tSU(1)
tH(2) TDI (INPUT) tSU(2)
tPW(1) TDO (OUTPUT) tD
tPW(1) TRS (INPUT)
Parameter TCK clock high time TCK clock low time TMS setup time before TCK TMS hold time after TCK TDI setup time before TCK TDI hold time after TCK TDO delay from TCK (Note 1) TRS Pulse Width
Symbol tPWH tPWL tSU(1) tH(1) tSU(2) tH(2) tD tPW(1)
Min 50 50 3.0 2.0 3.0 2.0 20
Max
Unit ns ns
22 -
ns ns ns ns ns ns
Note 1: The output time (TDO) is measured with a maximum of 75 pF load capacitance.
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DATA SHEET OPERATION
The following sections detail the internal operation of the Quad E1 Mapper. BUS INTERFACE MODES The Quad E1 Mapper supports the following bus modes of operation: - Drop Mode - Single Unidirectional Ring Mode - Multiplexer Mode - Dual Unidirectional Ring Mode Drop Mode
QE1M TXC-04252
In the drop mode of operation, a TU/VT is terminated from either the A or B Drop bus to the receive output of one of the four ports, without a return path in the transmit direction. Single Unidirectional Ring Mode In the single unidirectional ring mode of operation, a TU/VT is dropped from the A (or B) Drop bus, with the return path the A (or B) Add bus. Timing for the TU/VT to be added to the A (or B) Add bus is derived from either the A (or B) Drop bus, or from the A (or B) Add bus. Multiplexer Mode In the multiplexer mode of operation, a TU/VT is dropped from the A (or B) Drop bus, with the return path the B (or A) Add bus. Timing for the TU/VT to be added to the A (or B) Add bus is derived from either the A (or B) Drop bus, or from the A (or B) Add bus. Dual Unidirectional Ring Mode In the dual unidirectional ring mode of operation, a TU/VT is dropped from the A (or B) Drop bus, with the return path both the A and B Add buses. Timing for the TU/VT to be added to the A (or B) Add bus is derived from either the A (or B) Drop bus, or from the A (or B) Add bus.
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QE1M TXC-04252
BUS MODE SELECTION
DATA SHEET
TU/VT bus mode selection is performed by the control bits defined in the table shown below. The n represents the port number (1-4). Note: Both the A and B Add buses power up in the high impedance state. A 0 must be written to control bits AAHZE and BAHZE for normal add bus operation. Mode Type Dropping only, from A Dropping only, from B Adding only, to A Adding only, to B Single unidirectional ring Single unidirectional ring Multiplexer, A in, B out Multiplexer, B in, A out Dual unidirectional ring Dual unidirectional ring TnSEL1 0 0 0 0 0 0 1 1 1 1 TnSEL0 0 0 1 1 1 1 0 0 1 1 RnSEL 0 1 0 1 0 1 0 1 0 1 DROP from Bus A B Add-only (2) Add-only (2) A B A B A B ADD to Bus Drop-only (1) Drop-only (1) A B A B B A A and B B and A
Notes: 1. When the drop-only mode is selected, the ability to add a TU/VT is disabled, and the add bus is tri-stated. 2. The add-only feature is enabled by writing a 1 to control bit FRDISn. The FEBE value and RDI states are transmitted as zero. However, the microprocessor can send an RDI, if required.
Bus Mode Selection for Port n
SDH/SONET ADD/DROP MULTIPLEXING FORMAT SELECTIONS The control bit settings for format selection are given in the table shown below. When the STS-1 format is selected, the buses are configured to operate at a bus rate of 6.48 Mbyte/s, instead of 19.44 Mbyte/s for VC-4/AU-3/STS-3 formats.
Format STS-1 Format STS-3 Format STM-1 AU-3 Format STM-1 TUG-3/VC-4 Format
MOD1 0 0 1 1
MOD0 0 1 0 1
Format Selection
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DATA SHEET
DROP TU/VT SELECTION
QE1M TXC-04252
The TU-12 (VT2) number selection register labels (RTUNn), which consist of seven bits, are given in the following table. An out of range value forces a high impedance state at the E1 receive interface. In addition, the FEBE and RDI states will be transmitted as zeros.
Locations 04CH (port 1), 07CH (port 2), 0ACH (port 3), 0DCH (port 4) Bit 6 5 4 3 2 1 0 Meaning No TU/VT Selected STS-1 AU-3/TUG-3 A, STS-1 #1 AU-3/TUG-3 B, STS-1 #2 AU-3/TUG-3 C, STS-1 #3 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 0 1 1 TU/VT Selection 0 1 0 1 TU/VT Group Number 1 TU/VT Group Number 2 TU/VT Group Number 3 TU/VT Group Number 4 TU/VT Group Number 5 TU/VT Group Number 6 TU/VT Group Number 7 No TU/VT Selected TU/VT Number 1 TU/VT Number 2 TU/VT Number 3 AU-3/TUG-3 or STS-1 ID 0 0 0 1 1 0 0 1 0 1 TU/VT Group Number 0 0 0 TU/VT Number 0 0
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QE1M TXC-04252
ADD TU/VT SELECTION
DATA SHEET
The TU-12 (VT2) number selection register labels (TTUNn), which consist of seven bits, are given in the following table. An out of range value forces a high impedance state on the add bus.
Locations 04DH (port 1), 07DH (port 2), 0ADH (port 3), 0DDH (port 4) Bit 6 5 4 3 2 1 0 Meaning No TU/VT Selected STS-1 AU-3/TUG-3 A, STS-1 #1 AU-3/TUG-3 B, STS-1 #2 AU-3/TUG-3 C, STS-1 #3 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 0 1 1 TU/VT Selection 0 1 0 1 TU/VT Group Number 1 TU/VT Group Number 2 TU/VT Group Number 3 TU/VT Group Number 4 TU/VT Group Number 5 TU/VT Group Number 6 TU/VT Group Number 7 No TU/VT Selected TU/VT Number 1 TU/VT Number 2 TU/VT Number 3 AU-3/TUG-3 or STS-1 ID 0 0 0 1 1 0 0 1 0 1 TU/VT Group Number 0 0 0 TU/VT Number 0 0
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DATA SHEET
BUS TIMING
QE1M TXC-04252
Timing for adding a TU/VT to the add bus is derived from the like-named drop bus, or from the like-named add bus. Bus timing may be selected by using a lead, or through software. Upon power-up or a device reset, the SBTEN (Software Bus Timing Enable) control bit is reset to 0 and the ABUST lead controls bus timing selection. To enable the software to control timing, the SBTEN control bit must be first written with a 1, which will override the state placed on the ABUST lead. When SBTEN is 1, bus timing (add or drop bus timing) is controlled by the DRPBT control bit. The various states associated with the bus timing selection are shown in the table below.
ABUST lead Low High X X
Note: X = Don't Care
SBTEN 0 0 1 1
DRPBT X X 0 1
Action Add bus timing selected by ABUST lead. Drop bus timing selected by ABUST lead. Add bus timing selected by DRPBT bit. Drop bus timing selected by DRPBT bit.
Bus Timing Selection
UNEQUIPPED OPERATION The QE1M is capable of sending an unequipped channel or unequipped supervisory channel in all add modes of operation. Generally a channel which has either the UCHnE bit or both the UCHnE and USCHnE bits set in the port provisioning registers will add an unequipped channel or unequipped supervisory channel for the TU/VT selected. An unequipped channel has a TU/VT pointer consisting of a valid NDF, size bits equal to 01, and a fixed pointer value of 105. The remaining VT overhead bytes and the payload are sent as zeros. The unequipped supervisory channel has an identical pointer to the unequipped channel, but sends a valid J2 byte, and valid BIP-2 bits and RDI-bit in V5, and valid RDI-bits in Z7. The QE1M also sends a valid Z6 byte. The V5, RDI, Z7 RDI, and Z6 bytes can be set to zero by other control bits if they are not required. There are some differences in operation based on the UEAME bit in register 014H. The following table describes these differences.
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DATA SHEET
Unequipped Channel Generation UCHnE/USCHnE UEAME Add/Drop Mode Mux Single Unidirectional Ring Bidirectional Ring Drop Only Mux Single Unidirectional Ring 0 Bidirectional Ring Drop Only 1 Mux Single Unidirectional Ring 1 Bidirectional Ring Drop Only Drop From A B A B A B A B A B A B A B A B A B A B A B A B A add High-Z Normal Normal High-Z Normal Normal High-Z High-Z Unequipped2 Normal Unequipped High-Z Unequipped Unequipped High-Z High-Z High-Z Unequipped2 Unequipped High-Z Unequipped Unequipped High-Z High-Z B add Normal High-Z High-Z Normal Normal Normal High-Z High-Z Normal Unequipped2 High-Z Unequipped Unequipped Unequipped High-Z High-Z Unequipped2 High-Z High-Z Unequipped Unequipped Unequipped High-Z High-Z
0
X1
Notes: 1. X = Don't Care (0 or 1). 2. Only Multiplexed Mode is effected by the UEAME control bit. All other modes operate the same way regardless of the state of the UEAME control bit.
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DATA SHEET
DROP BUS MULTIFRAME ALIGNMENT
QE1M TXC-04252
V1 byte alignment in the receive direction (from the drop bus) is established by using the H4 byte or the V1 reference pulse in the ADC1J1V1 and BDC1J1V1 signal. Depending on the format, one or three V1 pulses will be present in this signal. When the H4 byte is used to establish V1 byte alignment, the V1 pulse does not have to be present in the ADC1J1V1 or BDC1J1V1 signal. Writing a 1 to control bit DV1SEL selects the V1 pulse in the ADC1J1V1 and BDC1J1V1 signal to be used to establish the V1 byte location reference, while a 0 selects the H4 byte as the multiframe detector for establishing the V1 reference. The H4 multiframe detection circuits are disabled when the V1 pulse is used in place of the H4 byte. For STM-1 VC-4 operation, a single V1 pulse must occur three drop bus clock cycles every four frames following the J1 pulse. For STM-1 AU3/STS-3 operation, three V1 pulses must be present every four frames. Each V1 pulse must be present three clock cycles after the corresponding J1 pulse, when the SPE signal is high. For example, in a VC-4 signal, the J1 pulse identifies the J1 byte location (defined as the starting location for the VC-4) in the POH bytes. In the next column (first clock cycle) all the rows are assigned as fixed stuff. Similarly, in the next column (second clock cycle) all the rows are assigned as fixed stuff. The next column (third clock cycle) defines the start of TUG-3 A. This column is where the V1 pulse occurs every four frames. However, the actual V1 byte occurs six clock cycles after the V1 pulse. For STS-1 operation, one V1 pulse must be present. The V1 pulse must occur on the next clock cycle after J1, and when the SPE signal is high. The J1 pulse identifies the J1 byte location (defined as the starting location for the STS-1) in the POH bytes. The next column (first clock cycle) defines the VTs starting location. Thus, the V1 pulse identifies the starting location of the first V1 byte in the signal. The rest of the V1 bytes for the 21 VT2s are also aligned with respect to the V1 pulse. The timing relationships between J1, V1, and other signals are shown in the Timing Characteristics section. The H4 byte is used to identify the location of the V1 byte as shown in 18 below: 2048 kbit/s TU/VT H4 (XXXX XX00) Of Previous SPE V1 35 Bytes H4 (XXXX XX01) V2 35 Bytes H4 (XXXX XX10) V3 35 Bytes H4 (XXXX XX11) V4 35 Bytes Figure 18. H4 Byte Floating VT Mode Bit Allocation The H4 byte is monitored for multiframe alignment when enabled. Loss of multiframe alignment is declared (AsDH4E, BsDH4E) if two or more H4 byte values differ from those of a 2-bit counter for two consecutive multiframes. Recovery occurs when four consecutive sequential H4 byte values are detected once.
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QE1M TXC-04252
ADD BUS MULTIFRAME ALIGNMENT
DATA SHEET
When drop bus timing is selected, add bus V1 alignment is based on the drop bus V1 pulse (A/BDC1J1V1) if DV1SEL is 1, or on the V1 reference signal that is generated by the H4 multiframe detectors in the drop bus side if DV1SEL is 0. When add bus timing is selected and a 0 is written to control bit DV1REF, V1 byte alignment for the add bus is established by using the V1 pulses that must be present in the A/BAC1J1V1 signal. When add bus timing is selected and a 1 is written to control bit DV1REF, V1 byte alignment for the add bus is determined by the drop bus V1 reference from either the A/BDC1J1V1 signal (if DV1SEL is 1), or from the internal V1 reference signal generated by the H4 multiframe detector in the drop bus direction (if DV1SEL is 0). The V1 pulse that is present in the A/BAC1J1V1 signal is ignored. Extreme care must be taken when using this V1 selection mode to prevent add bus V1 byte alignment slips. The control bit selection for both V1 add and drop bus byte alignment is described in the table below. Bus Timing Mode Drop bus timing selected DV1REF 0 DV1SEL 0 Action Drop bus A/B H4 multiframe detector determines dropped TU/VT V1 byte starting location, and added TU/VT V1 byte starting location. V1 pulse in drop bus A/BDC1J1V1 signal ignored. Drop bus V1 pulse in the A/BDC1J1V1 signal determines dropped TU/VT V1 byte starting location, and added TU/VT V1 byte starting location. A/B drop bus H4 multiframe detector disabled. Drop bus A/B H4 multiframe detector determines dropped TU/VT V1 byte starting location. V1 pulse in drop bus A/BDC1J1V1 signal ignored. Add bus V1 alignment determined by the V1 pulse in the add bus A/BAC1J1V1 signal. Drop bus V1 pulse in the A/BDC1J1V1 signal determines dropped TU/VT starting location. Drop bus H4 multiframe detector disabled. Add bus V1 alignment determined by the V1 pulse in the add bus A/BAC1J1V1 signal. Drop bus A/B H4 multiframe detector determines dropped TU/VT V1 byte starting location. V1 pulses in drop bus A/BDC1J1V1 and add bus A/BAC1J1V1 signals are ignored. Add bus V1 alignment determined by the internal V1 pulse generated by the drop bus A/B H4 byte detector. Drop bus V1 pulse in the A/BDC1J1V1 signal determines dropped TU/VT V1 byte starting location, A/B drop bus H4 multiframe detector disabled. V1 pulse in add bus A/BAC1J1V1 signal is ignored. Add bus V1 alignment determined by the V1 pulse in the drop bus A/BDC1J1V1 signal.
Drop bus timing selected
0
1
Add bus timing selected
0
0
Add bus timing selected
0
1
Add bus timing selected
1
0
Add bus timing selected
1
1
Note: X = Don't Care. Bus timing mode is selected via lead ABUST and control bits SBTEN, DRPBT, as described earlier.
Add and Drop Bus V1 Reference Selection
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DATA SHEET
PERFORMANCE COUNTERS
QE1M TXC-04252
All performance counters are saturating, with the counters stopping at their maximum count. A counter is reset to zero by a hardware or software device reset, and when it is read by the microprocessor. The performance counters for port n are also reset when a 1 is written to control bit RnSETC. This bit is self-clearing, and does not require the microprocessor to write a 0 into its location. Counts that occur during the read cycle are held and updated afterwards. For a 16-bit counter, the low order byte must be read first, followed by reading the high order byte before the corresponding low order byte for another port is read. ALARM STRUCTURE All alarm indications are reported as unlatched and latched status bits. The latched bit of an alarm can be set on the positive transitions, negative transitions, both positive and negative transitions, or positive levels of the alarm. Reading a latched alarm bit clears the bit to 0. When control bit LATEN (address 011H, bit 4) is written with a 1, the latching of alarm transitions is enabled. Control bits IPOS and INEG (address 012H, bits 5 and 4) should be programmed to select the transition(s) on which latched bits are set. When LATEN is written with a 0, the latched bits are set on positive levels of the alarms. The IPOS and INEG bits are disabled when LATEN is set to 0. Alarm Hierarchy Mask Since multiple alarms at various levels can be detected simultaneously, a hierarchical masking scheme is employed in the QE1M. The QE1M hierarchical mask effectively eliminates the confusion caused by the simultaneous reporting of multiple alarms and speeds up the identification of the alarm origins. The following table shows the hierarchical masking of unlatched low level alarms by high order alarms (depending on the Drop Bus selected and the Port selected). Masked cells indicate the lower level alarm masked by the high order alarms. For example: low level alarms J2LOL and J2TIM are masked when any of the following high order alarms/conditions are active: DLOC, OOR, UAISI, DH4E, AIS, LOP or SLER. Low Level Alarms masked by High Order Alarms High Order Alarms or Conditions DLOC OOR1 UAISI2, DH4E3 AIS, LOP Signal Label =001 or =000 SLER5 TCLM4 UAISI DH4E LOP AIS NDF SIZE * * * SLER RFI UNEQ J2LOL J2TIM RDIS RDIP RDIC * * * * TCUQ TCAIS TCLM * * * * TCLL TCTM TCODI TCRDI * * * *
*
* * * * *
* * * *
* * * *
* *
Notes: 1. OOR: Receive TU/VT Out Of Range is the condition when the receive TU/VT select bits (registers 0x4C, 7C, AC, DC) are set to an invalid value in which no TU/VT is selected (e.g. 0x00). There is no alarm bit to indicate this condition. 2. When control bit HEAISE is 1 3. When control bit DV1SEL is 0 4. When control bit TCnEN is 1 5. When control bit 1BnRDI = 0 When control bit 1BnRDI = 1, then J2 Message Tracking is still enabled and SLER alarm will not mask J2LOL and J2TIM.
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QE1M TXC-04252
INTERRUPT STRUCTURE
DATA SHEET
The interrupt indication register (address 020H) contains the global software interrupt bit INT and other interrupt indication bits. Each interrupt indication bit has an associated set of latched alarm bits. A mask bit is provided to enable the set of latched alarms to trigger their interrupt indication bit. For port alarms, the latched alarms of each port are further divided into several groups. A second level of mask bit is provided for each of these groups to mask out the interrupt indication bit of the port. For each interrupt indication bit, if its interrupt mask bits are 1, and one or more of its associated latched alarm bits are set, the interrupt indication bit will become 1; which in turn causes the software interrupt indication bit INT to become 1. The QE1M also generates a hardware interrupt at the tristate 8mA interrupt lead INT(INT/IRQ), lead 152 or D6, provided the hardware interrupt enable bit (HWDIE) is 1. Addresses 016H and 021H are the first set of interrupt mask registers. The additional mask registers for the port alarms are contained in addresses 017H, 018H and 019H. Upon power-up, when the RESET bit (bit 7 in address 015H) is written with a 1, or an active low is placed on the RESET lead (lead 155 or C5), all the interrupt mask bits are cleared to 0. They must be initialized to 1 in order to enable the interrupt indication bits. Control bits IPOS, INEG and LATEN should also be programmed to determine how the latched alarms are to be set. Consider alarm AnAIS. Assume that HWDIE is 1, the interrupt masks for AnAIS are 1, the control bits IPOS and LATEN are 1, and control bit INEG is 0. Since AnAIS is a port alarm, interrupt mask bit PnMSK and the second level mask bit RPTnA should be set to 1. A positive transition on AnAIS causes the latched bit of AnAIS to be set, which in turn sets the interrupt indication bit PORTn. Then, both software and hardware interrupts occur. When an interrupt occurs, the external microprocessor can determine the alarm that caused the interrupt by reading the latched alarm registers that correspond to the interrupt indication bit and interrupt mask bit. The read cycles allow the microprocessor to determine what alarm has been set. When the register containing the latched alarm (e.g., AnAIS) has been read, the latched alarm bit is cleared, releasing the software interrupt (INT and PORTn returning to 0) and hardware interrupt. If there is more than one alarm in more than one alarm register, each of the corresponding latched alarm registers must be read before the interrupt is released. In addition, the hardware and software interrupt may be released by writing a 0 to the mask bits that correspond to the interrupt indication register. For AnAIS, the interrupt can be masked by writing 0 to PnMSK or to the RPTnA bits.
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DATA SHEET
Interrupt Registers
Address 020H
INT Interrupt Indication Register (Address 020H)
QE1M TXC-04252
EXTCK
ASIDE
BSIDE
PORT4
PORT3
PORT2
PORT1
Interrupt Mask Register (Address 016H, 021H)
016H 021H
0 0
0 ECKMSK
0 ASMSK
0 BSMSK
0 P4MSK
0 P3MSK
0 P2MSK
SPTMSK P1MSK
Additional Interrupt Mask Registers (Addresses 017H, 018H, 019H)
017H 018H 019H
RPT4A TFIFO4A TPORT4
RPT4B TFIFO4B TPORT3
RPT3A TFIFO3A TPORT2
RPT3B TFIFO3B TPORT1
RPT2A TFIFO2A RFIFO4
RPT2B TFIFO2B RFIFO3
RPT1A TFIFO1A RFIFO2
RPT1B TFIFO1B RFIFO1
Interrupt Indication ASIDE Registers (Addresses 022H, 024H) A Side Drop/Add Alarms (ASIDE) 022H 024H ADLOC LEXTC AALOC 0 ADPAR 0 0 0 0 0 A3UAISI A3DH4E A2UAISI A2DH4E A1UAISI A1DH4E
Interrupt Indication BSIDE Registers (Addresses 026H, 028H) B Side Drop/Add Alarms (BSIDE) 026H 028H BDLOC SPTLOC BALOC WDTEXP BDPAR 0 0 PERR 0 0 B3UAISI B3DH4E B2UAISI B2DH4E B1UAISI B1DH4E
Interrupt Indication PORTn Registers (Addresses 030H, 04EH, 05AH, 03AH, 05EH, 05CH, 044H for Port 1) Port n Alarms (PORTn) 030H 060H 090H 0C0H 04EH 07EH 0AEH 0DEH 05AH 08AH 0BAH 0EAH 03AH 06AH 09AH 0CAH 05EH 08EH 0BEH 0EEH 05CH 08CH 0BCH 0ECH 044H 074H 0A4H 0D4H AnAIS AnRDIP AnTCUQ BnAIS BnRDIP BnTCUQ RnFFE AnLOP AnRDIC AnTCAIS BnLOP BnRDIC BnTCAIS 0 AnSIZE 0 AnTCLM BnSIZE 0 BnTCLM 1 AnNDF 0 AnTCLL BnNDF 0 BnTCLL TAnFE AnRDIS AnJ2LOL AnTCTM BnRDIS BnJ2LOL BnTCTM TBnFE AnRFI AnJ2TIM AnTCODI BnRFI BnJ2TIM BnTCODI TnLOS AnUNEQ 0 AnTCRDI BnUNEQ 0 BnTCRDI TnLOC AnSLER 0 0 BnSLER 0 0 TnDAIS
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QE1M TXC-04252
DATA SHEET
Alarms, Interrupt Masks and Interrupt Indications A Side and B Side Alarms and Interrupts Latched Alarm Address 022H Alarm Name ADLOC AALOC ADPAR 0 0 A3UAISI A2UAISI A1UAISI 024H LEXTC 0 0 0 0 A3DH4E A2DH4E A1DH4E 026H BDLOC BALOC BDPAR 0 0 B3UAISI B2UAISI B1UAISI 028H SPTLOC WDTEXP 0 PERR 0 B3DH4E B2DH4E B1DH4E
Note 1. The SPOT alarm does not have an interrupt indication bit but it can still cause both software interrupt (INT bit) and hardware interrupt (INT/IRQ lead).
Interrupt Mask or (016H or 021H) ASMSK
Additional Interrupt Mask (if any)
Interrupt Indication Bit (020H) ASIDE
ECKMSK
EXTCK
ASMSK
ASIDE
BSMSK
-
BSIDE
SPTMSK
-
(Note 1)
BSMSK
-
BSIDE
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A Side and B Side Port n Alarms and Interrupts
Latched Alarm Address 030 port 1 060 port 2 090 port 3 0C0 port 4 Interrupt Mask (021H) PnMSK Additional Interrupt Interrupt Indication Mask Bit (if any) (020H) (017H) RPTnA PORTn Latched Alarm Address 03A port 1 06A port 2 09A port 3 0CA port 4 Interrupt Mask (021H) PnMSK
QE1M TXC-04252
Alarm Name
Alarm Name
Additional Interrupt Interrupt Indication Mask Bit (if any) (020H) (017H) RPTnB PORTn
AnAIS AnLOP AnSIZE AnNDF AnRDIS AnRFI AnUNEQ AnSLER
BnAIS BnLOP BnSIZE BnNDF BnRDIS
RFIE (Note 1) RPTnA
BnRFI BnUNEQ BnSLER 05E port 1 08E port 2 0BE port 3 0EE port 4 BnRDIP BnRDIC 0 0 BnJ2LOL BnJ2TIM 0 0 05C port 1 BnTCUQ 08C port 2 BnTCAIS 0BC port 3 0EC port 4 BnTCLM BnTCLL BnTCTM BnTCODI BnTCRDI 0
RFIE (Note 1) RPTnB
04E port 1 07E port 2 0AE port 3 0DE port 4
AnRDIP AnRDIC 0 0 AnJ2LOL AnJ2TIM 0 0
05A port 1 AnTCUQ 08A port 2 AnTCAIS 0BA port 3 0EA port 4 AnTCLM AnTCLL AnTCTM AnTCODI AnTCRDI 0
Note 1. RFIE (address 012H, bit 3) is a common control bit for all four ports. A 1 enables the RFI indication to cause an interrupt. RPTnA or RPTnB is not required to be set to 1 to enable the interrupt for the RFI indication. A 0 disables an RFI indication from causing an interrupt.
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QE1M TXC-04252
DATA SHEET
Common Port n Alarms and Interrupts
Latched Alarm Address 044 port 1 074 port 2 0A4 port 3 0D4 port 4 Additional Interrupt Mask Interrupt Mask (021H) (if any) (018H or 019H) PnMSK RFIFOn Interrupt Indication Bit (020H) PORTn
Alarm Name
RnFFE 0 1 TAnFE TBnFE TnLOS TnLOC TnDAIS
TFIFOnA TFIFOnB TPORTn
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Interrupt and Alarm Control Bit Summary IPOS 012H: 5 0 X INEG 012H: 4 0 X HWDIE 014H: 0 0 X LATEN 011H: 4 1 0 Interrupt Mask Bit X 0 Action on an Alarm
QE1M TXC-04252
No alarm event indication, or interrupt register indication. Alarm event register sets on positive levels of an alarm; no software or hardware interrupt indications. Alarm event register sets, and software interrupt indication occurs, on positive levels of the alarm; no hardware interrupt. Alarm event register sets, and software and hardware interrupt indications occur, on positive levels of the alarm. Alarm event register sets on positive transitions of the alarm; no software or hardware interrupt indications. Alarm event register sets, and software interrupt indication occurs, on positive transitions of the alarm; no hardware interrupt. Alarm event register sets, and software and hardware interrupt indications occur, on positive transitions of the alarm. Alarm event register sets on negative transitions of the alarm; no software or hardware interrupt indications. Alarm event register sets, and software interrupt indication occurs, on negative transitions of the alarm; no hardware interrupt. Alarm event register sets, and software and hardware interrupt indications occur, on negative transitions of the alarm. Alarm event register sets on positive and/or negative transitions of the alarm; no software or hardware interrupt indications. Alarm event register sets, and software interrupt indication occurs, on positive and/or negative transitions of the alarm; no hardware interrupt. Alarm event register sets, and software and hardware interrupt indications occur, on positive and/or negative transitions of alarm.
X
X
0
0
1
X
X
1
0
1
1
0
X
1
0
1
0
0
1
1
1
0
1
1
1
0
1
X
1
0
0
1
0
1
1
0
1
1
1
1
1
1
X
1
0
1
1
0
1
1
1
1
1
1
1
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QE1M TXC-04252
SDH/SONET AIS DETECTION
DATA SHEET
The Quad E1 Mapper can detect an upstream AIS condition using the TOH H1/H2 (pointer) bytes or the TOH E1 (order wire) byte. When control bit SE1AIS (address 014H, bit 3) is 0, the H1/H2 bytes are monitored for an upstream AIS condition. When the MOD control bits (address 010H, bits 7 and 6) select the VC-4/TUG-3 format, the H11 and H21 bytes only are monitored for AIS. The monitoring of AIS in the two other H1n/H2n bytes is disabled. When the MOD control bits select the STS-3 or AU-3 format, each set of the three H1/H2 bytes per A Drop and B Drop buses are monitored for an AIS indication. Each of the three H1/H2 pointer bytes corresponds to the like-numbered AU-3/STS-1 signal (n=1-3). When the MOD control bits select the STS-1 format, the H1/H2 bytes per A Drop and B Drop buses are monitored for an AIS indication. If all ones are detected in the H1/H2 bytes (whose location is determined by the C1 pulse) for three consecutive frames, the alarm bits AsUAISI in addresses 022H and 023H (A bus detected H1/H2 or E1 byte upstream AIS) or BsUAISI in addresses 026H and 027H (B bus detected H1/H2 or E1 byte upstream AIS) will set. Recovery occurs when a normal NDF (bits 1 through 4) in H1 is detected for three consecutive frames. A normal NDF is defined as a 0110, but 1110, 0010, 0100 and 0111 are also recognized as normal. The H1/H2 byte AIS detection circuits (when selected) for both the A and B Drop buses are disabled by writing a 0 to control bit HEAISE (address 013H, bit 7). When control bit SE1AIS is 1, the E1n bytes are monitored for an upstream AIS condition. When the MOD control bits select the VC-4/TUG-3 format, the E11 byte in both buses is monitored for AIS. The detection of the upstream AIS indication in the E12 and E13 bytes is disabled. When the MOD control bits select the AU-3/STS-3 format, each of the three E1n bytes in the A and B Drop buses are monitored for AIS. Each of the three E1n bytes corresponds to the like-numbered AU-3/STS-1 signal. For STS-1 operation, the single E1 byte is checked for the upstream AIS indication. Majority logic is used to determine if an E1n byte is carrying an upstream AIS indication. If 5 or more ones (at least 5 bits equal to 1 out of the 8 bits) are detected once in a A/B Drop bus E1n byte (whose locations are determined by the C1 pulse), the alarm bit AsUAISI (A bus detected H1/H2 or E1 Byte AIS) or BsUAISI (B bus detected H1/H2 or E1 Byte AIS) is set. Recovery occurs when 4 or more zeros (at least 4 bits equal to 0 out of the 8 bits) are detected once. The E1n byte AIS detection circuits (when selected) for both the A and B Drop buses are disabled by writing a 0 to control bit HEAISE.
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TU/VT POINTER TRACKING
QE1M TXC-04252
The starting location of the V1 byte is determined by either the V1 pulses in the A/BC1J1V1 signals or the H4 multiframe detection circuits. The TU/VT pointer bit assignment for the V1 and V2 bytes is shown below. The alignment is necessary to determine the starting locations of the V5 byte and the other bytes that are carrying the 2048 kbit/s format. V1 Byte 1 N 2 N 3 N 4 N 5 6 7 I 8 D 1 I 2 D 3 I SS-bits V2 Byte 4 D 5 I 6 D 7 I 8 D
I = Increment Bit D = Decrement Bit N = New Data Flag Bit (enabled = 1001 or 0001/1101/1011/1000, normal or disabled = 0110 or 1110/0010/0100/0111) Negative Justification: Inverted 5 D-bits and accept majority rule Positive Justification: Inverted 5 I-bits and accept majority rule SS-bits (VT Size) = 10 for 2048 kbit/s Pointer Bytes Bit Assignment The pointer value is a binary number with a range of 0 to 139 for the 2048 kbit/s format. The pointer offset indicates the offset from the V2 byte to the first byte in the TU-12/VT2 mapping. The pointer bytes are not counted in the offset calculation. The pointer offset arrangement for this format is shown below. 2048 kbit/s TU-12/VT2 V1 105 106-138 139 V2 0 1-33 34 V3 35 36-68 69 V4 70 71-103 104 TU/VT Pointer Offset Locations
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QE1M TXC-04252
DATA SHEET
Eight independent pointer-tracking state machines are used in the Quad E1 Mapper, one for each of the A and B buses in each of the four ports 1, 2, 3, and 4. The pointer tracking algorithm is illustrated in 19. The pointer tracking state machine is based on the pointer tracking machine found in the latest ETSI requirements, and is also valid for both Bellcore and ANSI. When control bit PTALTE at address 014H, bit 1 is 0, the transition from AIS to LOP is disabled (shown dotted), which is required in Bellcore recommendations.
3 x AIS_ind (Offset Undefined)
inc_ind (Incr. Offset) 3 x any_point 3 x new_point (Accept New Offset)
INC
NDF_enable (Accept New Offset) NDF_enable (Accept New Offset)
DEC
3 x AIS_ind (Offset Undefined)
3 x new_point (Accept New Offset) NDF_enable (Accept New Offset) 3 x new_point (Accept New Offset) 3 x any_point NDF_enable (Accept New Offset) 8 x inv_point (Offset Undefined) dec_ind (Decr. Offset) 3 x any_point
NDF
NORM
3 x new_point (Accept New Offset) 3 x AIS_ind (Offset Undefined) 3 x new_point (Accept New Offset)
3 x new_point (Accept New Offset)
3 x AIS_ind 8 x NDF_enable (Offset Undefined) (Offset Undefined)
LOP
8 x inv_point (Offset Undefined) NDF_enable (Accept New Offset) 3 x AIS_ind (Offset Undefined)
AIS
Figure 19. TU/VT Pointer Tracking State Machine
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REMOTE DEFECT INDICATIONS
QE1M TXC-04252
A 1-Bit/3-Bit RDI Selection bit - 1BnRDI (bit 4 in registers 048H, 078H, 0A8H, 0D8H) - has been added to allow the user to select between the Enhanced 3-Bit RDI (1BnRDI = 0) or Single Bit RDI (1BnRDI = 1). The following sections describe the differences. V5 and K4 (Z7) Byte Coding (for 3-Bit RDI) Bits 5, 6 and 7 in the K4 (Z7) byte, in conjunction with bit 8 in the V5 byte, provide a detection scheme which is compliant with earlier versions of the RDI standard and also with enhanced TU/VT RDI capability. The enhanced version of RDI allows the user to differentiate between server, connectivity, and payload defects. Bit 8 in V5 is set equal to bit 5 in K4 (Z7). Bit 7 in K4 (Z7) is set to the inverse of bit 6 of K4 (Z7) to distinguish the enhanced version of RDI from the old version of RDI. It should be noted that when bits 6 and 7 in K4 (Z7) are either 01 or 10, the RDI indication is also influenced by Bit 8 of V5, as shown in the table below. When bits 6 and 7 are either 00 or 11, then RDI is determined solely by bit 8 in V5. This allows detection of an RDI originating from older equipment that generates the RDI in the V5 byte. The following table lists the RDI defect indications carried in the V5 and K4 (Z7) bytes.
Bit 8 V5 Bit 5 K4 (Z7) 0 0 0
Bit 6 K4 (Z7) 0 0 1
Bit 7 K4 (Z7) 0 1 0
Definition No defect indications. No defect indications. Remote Payload Defect - Path Label Mismatch - Loss of Multiframe. No defect indications. Remote defect (old equipment). Remote Server Defect - VT Loss of Pointer - VT AIS detected - Upstream AIS detected (E1 or H1/H2 Bytes). Remote Connectivity Defect - Unequipped Signal Label - J2 Mismatch - J2 Loss of Lock Remote defect (old equipment).
0 1 1
1 0 0
1 0 1
1
1
0
1
1
1
RDI Bit Assignment for 3-Bit RDI
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QE1M TXC-04252
DATA SHEET
Receive RDI Detection and Recovery (for 3-Bit RDI) The RDI alarms are defined in the table below. The number of consecutive events for detection and recovery is controlled by control bit V5AL10 in address 014H, bit 2. The value of five is selected when the V5AL10 control bit is 0, and the value of ten is selected when the V5AL10 control bit is 1. AnRDIC BnRDIC 0 0 1 AnRDIP BnRDIP 0 1 0 AnRDIS BnRDIS 1 0 0 Action Remote Server Defect Indication, and old equipment RDI indication (Bit 8 in the V5 byte). Remote Payload Defect Indication. Remote Connectivity Indication.
RDI Alarm Definition for 3-Bit RDI Transmit RDI Generation (for 3-Bit RDI) An RDI is sent for the following unlatched alarm conditions in the V5 and K4 (Z7) overhead bytes of the VT added to the A or B Add bus, depending on the states of the RnSEL (active bus selected), TnSEL1 and TnSEL0 (bus enabled) control bits. The following examples apply to port 1, but corresponding examples for ports 2 through 4 may be constructed by substituting the port number digit for the 1-digit in the bit symbols (except DV1SEL). The variable s refers to the STS-1 or AU-3/TUG-3 identifier (s = 1 - 3). - When RDI enable (RDIEN) is 1, a Remote Server Defect Indication is sent for: - VT Loss of Pointer (A1LOP B1LOP) , - VT AIS (A1AIS, B1AIS) - A/B Drop Bus Upstream AIS in H1/H2 or the E1 byte (AsUAISI, BsUAISI), when HEAISE is 1 - Microprocessor writes a 1 to T1RDIS - When RDI enable (RDIEN) is 1, a Remote Payload Defect Indication is sent for: - A/B Drop H4 Error (AsDH4E, BsDH4E), when DV1SEL is 0 - Mismatch signal label (A1SLER, B1SLER) - Microprocessor writes a 1 to T1RDIP - When RDI enable (RDIEN) is 1, a Remote Connectivity Defect Indication is sent for: - Unequipped signal label (A1UNEQ, B1UNEQ), when UQAE is 1 - J2 Mismatch (A1J2TIM, B1J2TIM), when J21AISE is 1 - J2 Loss of Lock (A1J2LOL, B1J2LOL), when J21AISE is a 1 - Microprocessor writes a 1 to T1RDIC - When RDI enable (RDIEN) is 0, the microprocessor can control RDI generation: - Microprocessor writes a 1 to T1RDIS to generate remote server defect indication. - Microprocessor writes a 1 to T1RDIP to generate remote payload defect indication. - Microprocessor writes a 1 to T1RDIC to generate remote connectivity defect indication.
Note:The microprocessor may send an RDI by writing to the above control bits at any time, including the add-only mode. To prevent contention between the internal logic and full microprocessor control, the RDIEN control bit should be written with a 0 when microprocessor control is intended. The priority used for sending RDI if more than one of the microprocessor controls are set is: Server, Connectivity, and Payload. When RDIEN = 1 and no defects are generated then K4 bits 5,6,7 = 001.
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V5 and K4 (Z7) Byte Coding (for 1-Bit RDI)
QE1M TXC-04252
In the Receive (Rx) direction bit 8 in the V5 byte is used to detect Remote Defect Indications. Bits 5, 6, and 7 in the Rx K4(Z7) byte are not looked at for detecting RDI and can have any incoming value, 0 or 1. For transmitting 1-Bit RDI, bit 8 in V5 byte will be set as shown below and bits 5,6,7 in the K4(Z7) byte will be sent as 0. See table below:
Bit 8 V5 0 1
Bit 5 K4 (Z7) Bit 6 K4 (Z7) Bit 7 K4 (Z7) 0 0 0 0 0 0
Definition No defect indications. Remote Defect Indication.
RDI Bit Assignment for 1-Bit RDI Receive RDI Detection and Recovery (for 1-Bit RDI) The RDI alarm is defined in the table below. The number of consecutive events for detection and recovery is controlled by a Common Register - Provisioning Control bit V5AL10 (register 014H, bit 2). When V5AL10 = 0, the value is 5; when V5AL10 = 1, the value is 10. A Remote Defect Indication is indicated by alarm indication bit AnRDIS/BnRDIS. Alarm indication bits AnRDIP/BnRDIP and AnRDIC/BnRDIC are disabled and will always be equal to zero when 1-Bit RDI mode is selected. AnRDIC BnRDIC 0 0 AnRDIP BnRDIP 0 0 AnRDIS BnRDIS 0 1
Action No defect indications. Remote Defect Indication.
RDI Alarm Definition for 1-Bit RDI
Transmit RDI Generation (for 1-Bit RDI) An RDI is sent for the following unlatched alarm conditions in the V5 overhead byte of the VT added to the A or B Add bus, depending on the states of the RnSEL (active bus selected), TnSEL1 and TnSEL0 (bus enabled) control bits. The following examples apply to port 1, but corresponding examples for ports 2 through 4 may be constructed by substituting the port number digit for the 1-digit in the bit symbols (except DV1SEL). The variable s refers to the STS-1 or AU-3/TUG-3 identifier (s = 1 - 3). - When RDI enable (RDIEN) is 1, a remote defect indication (bit 8 in V5=1; bits 5,6,7 in K4(Z7)=0) is sent for: - VT Loss of Pointer (AnLOP BnLOP) , - VT AIS (AnAIS, BnAIS) - A/B Drop Bus Upstream AIS in H1/H2 or the E1 byte (AsUAISI, BsUAISI), when HEAISE is 1. - Unequipped Signal Label (AnUNEQ, BnUNEQ), when UQAE is 1. - J2 Loss of Lock (A1J2LOL, B1J2LOL), when J21AISE is a 1. - J2 Mismatch (A1J2TIM, B1J2TIM), when J21AISE is 1 - Microprocessor writes a 1 to T1RDIS to generate a Remote Defect Indication.
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QE1M TXC-04252
DATA SHEET
- When RDI enable (RDIEN) is 0, the microprocessor can control RDI generation: - Microprocessor writes a 1 to T1RDIS to generate Remote Defect Indication. Note: For 1-Bit RDI mode the following unlatched alarm conditions will not generate a Remote Defect Indication: - A drop H4 error (AsDH4E, BsDH4E), when DV1SEL is a 0. - Mismatch signal label (AnSLER, BnSLER). Note: For 1-Bit RDI mode the following microprocessor control bits are disabled and will not generate a Remote Defect Indication: - Microprocessor writes a 1 to TnRDIP . - Microprocessor writes a 1 to TnRDIC.
OVERHEAD COMMUNICATIONS BIT ACCESS Microprocessor access is provided for the eight overhead communications bits (O-bits) carried in the two justification control (JC) bytes in the multiframe format, e.g., in a 2048 kbit/s TU/VT, shown partially below. The bits in the justification control byte are numbered 1 through 8, starting with C1 as bit 1. Other Bytes J2 Byte JC Byte 1 C1 C2 O O O O R R
32 Bytes - Information R JC Byte 2 C1 R C2 R O R O Other Bytes O-bit Placement in a 2048 kbit/s TU/VT R O R O R R R R N2 (Z6) Byte
In the receive direction, the eight O-bits are stored in eight 8-bit registers (A and B for each group of 4 ports) and these registers are updated each frame. The two O-bit nibbles that form a byte in the registers for receiving and transmitting are from the same multiframe. Bits 3 through 0 in an O-bit register correspond to bits 3 through 6 (C1C2 OOOO RR) in the first justification control byte, and bits 7 through 4 in an O-bit register correspond to bits 3 through 6 in the second justification control byte, as shown below. Second Justification Control Byte Bit Register 3 7 4 6 5 5 6 4 First Justification Control Byte 3 3 4 2 5 1 6 0
O-bit Assignment Memory Map
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Receive J2 Byte Processing
QE1M TXC-04252
There are two possible received J2 message sizes, 16 bytes (ITU-T), or 64 bytes (ANSI). The QE1M is capable of dimensioning the transmit (and receive) RAM memory segment to the two sizes (16-Byte or 64-Byte). In addition, two modes of operation are provided for the 16-byte (ITU-T) format: a microprocessor read mode, and a compare read mode. The following table lists the various control states associated with J2 processing.
J2nSIZE 0
J2nCOM 0
Action Transmit and receive J2 segments are configured for the 16-byte J2 message size. Microprocessor read for the dropped J2 message. J2 alarms are disabled. Transmit and receive J2 segments are configured for the 16-byte J2 message size. For receiving, a 16-byte microprocessor message is written into a 16-byte segment for comparison against the received message. The written message must start with the multiframe indicator written into the starting location of the segment. Transmit and receive J2 segments are configured for the 64-byte J2 message size. Microprocessor read for the dropped J2 message. J2 alarms are disabled. The tandem connection feature must be disabled by setting TCnEN=0 for the port.
0
1
1
X
Note: X = Don't Care
The ITU-T defined 16-byte message consists of an alignment signal of (10000000 00000000) in the most significant bit (bit 1) of the message. The remaining 7 bits in each byte carry a data message, as illustrated below. Bit 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 3 4 5 6 7 8
16-Byte J2 Message
ITU-T 16-Byte J2 Message Format
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DATA SHEET
The definitions (ITU-T) shown below will be used in the following discussion of the J2 16-byte message comparison function. The memory locations apply to each memory group.
ITU-T Definitions
RxTI - Received TTI (Trail Trace Identifier) ExTI - Expected TTI (Trail Trace Identifier) AcTI - Accepted TTI (Trail Trace Identifier)
E1Mx16 Definitions
Incoming J2 trace message (Real Time) Microprocessor-written trace (reference) message. A Side (X50H - X5FH) B Side (XD0H - XDFH) Received stable trace message. A Side (X40H - X4FH) B Side (XC0H - XCFH)
The J2 16-byte message comparison works according to the following steps: 1. The microprocessor-written reference message (ExTI) locations should be initialized with the correct J2 16-byte message before enabling the J2 message comparison function. 2. The J2 message comparison function is then enabled (J2nCOM = 1; J2nSIZE = 0) and immediately the J2 Loss of Lock alarm will be active (J2nLOL = 1) and the J2 Trace Identifier Mismatch alarm will be inactive (J2nTIM = 0). This is the first step in the sequence - to initialize these alarms. 3. The incoming trace message (RxTI) is received, and the J2 comparison circuit searches for the J2 alignment pattern (Bit 1: 1000...0 pattern). 4. J2 alignment pattern is found and the Received stable trace message (AcTI) locations are updated with this incoming trace message (RxTI). 5. The incoming trace message (RxTI) is then checked for three consecutive 16-byte message repeats. 6. If an error occurs before step 5 is completed, the sequence repeats, starting at step 3 (searching for the alignment pattern). 7. If the incoming trace message (RxTI) repeats three times in a row (after the alignment pattern is detected) without an error then this is an in-lock condition, and the J2 Loss of Lock alarm is reset (J2nLOL = 0). Note that at this time the J2 mismatch alarm is still inactive (J2nTIM =0). 8. Once the incoming trace message is in-lock, the stable message (AcTI), is compared against the microprocessor-written reference message (ExTI), byte for byte, for 16 bytes (the length of the multiframe message). If they compare (AcTI = ExTI), a match is declared, with no mismatch alarm (J2nTIM = 0). If they do not compare (AcTI ExTI), a mismatch alarm is declared (J2nTIM = 1). A J2 mismatch alarm results in RDI and receive line AIS being sent continuously, when enabled. There is no Loss of Lock alarm (J2nLOL = 0) because the incoming trace message (RxTI) is stable. 10. If the incoming message (RxTI) changes for three consecutive 16-byte messages, a loss of lock alarm (J2nLOL = 1) occurs and the sequence starts again from the beginning (step 2). Summary of J2 Alarms: - J2 Loss of Lock (J2nLOL) is a comparison between the Received stable message (AcTI) and the Receive incoming (real time) message (RxTI). - Declare Lock (J2nLOL = 0) when AcTI = RxTI for 3 consecutive set of 16 bytes. - Loss of Lock (J2nLOL = 1) when AcTI RxTI on at least 1 byte in each of 3 consecutive 16-byte messages - J2 Trace Identifier Mismatch (J2nTIM) is a comparison between the Received stable message (AcTI) and the microprocessor-written reference message (ExTI). - Declare Mismatch (J2nTIM = 1) when AcTI ExTI on any byte once lock is declared.
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- Clear Mismatch (J2nTIM = 0) when AcTI = ExTI. See Note below. Note: A mismatch alarm is declared for the following reasons. 1. A valid mismatch alarm would be declared when the stable message (AcTI) does not match the reference message (ExTI). 2. An invalid mismatch alarm would be declared if the correct start-up procedure was not used and the reference message (ExTI) was not loaded before enabling the J2 comparison function. 3. Another reason for getting an invalid mismatch alarm would be if the reference message was written with the wrong message value. In any case if the incoming message is stable (or In-Lock - J2nLOL = 0) then the only way to clear the mismatch alarm would be to cause a Loss of Lock condition.
Suggested J2 16-byte Message Comparison Start-up Procedure: From Start-up: 1) At transmitting device - Send a "valid" message (TxTI). 2) At receive device - a) Load microprocessor-written reference message (ExTI) with a "valid" message. b) Enable J2 Message Comparison. Note: 1 and 2 are interchangeable If Changing Messages: 1) At receive device - Load microprocessor-written reference message (ExTI) with a "new valid" message. 2) At transmitting device - Send a "new valid" message (TxTI). Note: If 1 is not done before 2 then a mismatch alarm is declared. If this occurs it is not a valid mismatch (assuming that the messages are correct). Following the start-up procedure above will assure that the Trace Identifier Mismatch alarm only activates when the messages do not match. There is the possibility that a mismatch alarm will activate by not following the correct start-up procedure, upon which the following should be done: 1) At Receive device - verify that microprocessor-written (reference) message (ExTI) is correct 2) At Receive device - verify that the stable message (AcTI) is correct by examining J2nLOL. Since AcTI is written only once at the beginning of the algorithm, when searching for the J2 alignment pattern, if no Loss of Lock alarm is set then the incoming message RxTI is still the same valid message in AcTI. Now force a Loss of Lock condition by using the microprocessor to overwrite any byte of the stable message (AcTI) with a value that corrupts the alignment pattern (i.e., address X40=0x00). The Loss of Lock alarm will set, and then the re-start the algorithm from the beginning, which resets the mismatch alarm, and starts searching again for the alignment pattern.
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QE1M TXC-04252
DATA SHEET
N2 (Z6) Overhead Byte (Tandem Connection) The Tandem Connection feature is enabled for a TU/VT by writing a 1 to control bit TCnEN, when control bit J2nSIZE is a 0. When control bit TCnEN is written with a 0, the tandem connection feature is disabled. See address 051H, bit 4, in the Memory Map Descriptions section for more detail on TCnEN. The bit placement in a received N2 (Z6) byte is as shown below: Bit 1 BIP-2 2 3 1 4 AIS Indication 5 TC REI 6 TC OEI (FEBE) 7 8
Trace ID TC RDI/ODI
BIP-2, AIS INDICATION, TC REI AND TC OEI PROCESSING One or two errors may be detected in the TC BIP-2 comparison, and they are counted individually in an 8-bit counter when control bit BLOCK is written with a 0 (An TC BIP-2 Error Counter, Bn TC BIP-2 Error Counter). When control bit BLOCK is written with a 1, one or two parity errors are counted as a single block error. A tandem connection AIS alarm (AnTCAIS, BnTCAIS) is declared when bit 4 is equal to 1 for five consecutive frames. Recovery occurs when bit 4 is equal to 0 for five consecutive frames. An 8-bit counter (An TC REI Counter, Bn TC REI Counter) is provided for counting the number of REI bits received as equal to 1 in bit 5 (TC REI) in the N2 (Z6) byte. A REI indication (a 1) indicates that the distant end has detected one or two errors when the BIP-2 calculated for frame f-1 (all the bytes) is compared against the BIP-2 value carried in the N2 (Z6) byte in frame f. An 8-bit counter (An TC OEI Counter, Bn TC OEI Counter) is provided for counting the number of OEI bits received as equal to 1 in bit 6 (TC OEI) in the N2 (Z6) byte. An OEI indication (a 1) indicates that the distant end has detected one or two errors when the BIP-2 calculated for frame f-1 is compared against the BIP-2 value carried in the V5 byte in frame f. Bits 7 and 8 A multiframe alignment pattern, trace identifier message, TC RDI and TC ODI indications are assigned to bits 7 and 8 in the frames of a 76-frame structure, as shown below: Frame No. 1-8 9 - 12 13 - 16 17 - 20 65 - 68 69 - 72 73 74 75 76 N2 (Z6) Byte Definition Frame Alignment, 1111 1111 1111 1110 TC Trace ID Byte No. 0 (1 C1 C2 C3 C4 C5 C6 C7) TC Trace ID Byte No. 1 (0 X X X X X X X) TC Trace ID Byte No. 2 (0 X X X X X X X) TC Trace ID Byte No. 14 (0 X X X X X X X) TC Trace ID Byte No. 15 (0 X X X X X X X) Bit 7 = 0, Bit 8 = TC RDI Bit 7 = TC ODI, Bit 8 = 0 Bit 7 = 0, Bit 8 = 0 Bit 7 = 0, Bit 8 = 0
21 - 24 thru 61 - 64 TC Trace ID Bytes No. 3 thru 13
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QE1M TXC-04252
Loss of multiframe (status bits AnTCLM, BnTCLM) occurs when four consecutive Frame Alignment Signals (1111 1111 1111 1110) are detected in error (i.e., one or more error in each FAS). Multiframe alignment is recovered when three consecutive non-errored FAS are found. The TC trace identifier message comparison is based on the same state machine as that used for the 16-byte J2 message. If the message is not locked, an AnTCLL or BnTCLL alarm is declared. After TC lock is established, a comparison is performed between the microprocessor-written TC and the contents of the incoming message. The message consists of TC Trace ID bytes 0 to 15. A TC Trace Identifier Mismatch (AnTCTM, BnTCTM) alarm is declared when any byte does not match. Recovery occurs when there is a match between the microprocessor message and the accepted message. Bit 8 in frame 73 is defined as a Tandem Connection Remote Defect Indication (TC RDI). A TC RDI alarm occurs when a 1 has been detected in bit 8 in frame 73 for 5 consecutive multiframes (where each multiframe is 38 ms). The TC RDI alarm state is exited when bit 8 is equal to 0 for 5 consecutive multiframes. An alarm indication is reported as AnTCRDI or BnTCRDI. Bit 7 in frame 74 is defined as a Tandem Connection Outgoing Defect Indication (TC ODI). A TC ODI alarm occurs when a 1 has been detected in bit 7 in frame 74 for 5 consecutive multiframes (where each multiframe is 38 ms). The TC ODI alarm state is exited when bit 7 is equal to 0 for 5 consecutive multiframes. An alarm indication is reported as AnTCODI or BnTCODI. Tandem Connection Unequipped Status Unequipped Tandem Connection detection is provided. Five or more consecutive received tandem connection N2 (Z6) bytes equal to XX00 0000 result in a TC unequipped indication (AnTCUQ, BnTCUQ). The alarm state is exited when five or more consecutive received tandem connection N2 (Z6) bytes are not equal to XX00 0000. Note that bits 1 and 2 of the N2 (Z6) byte are masked (shown as X) and do not affect the indication.
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QE1M TXC-04252
TUG-3 NULL POINTER INDICATOR
DATA SHEET
For STM-1 TUG-3 format, the Quad E1 Mapper has the option to generate and transmit a Null Pointer Indicator (NPI) for one or more of the TUG-3s, as shown below.
TUG-3A 1 N P I 86 1 N P I TUG-3B 86 1 N P I TUG-3C 86
VC-4 P O H
1
261
NPI Structure Three control bits (NPIA, NPIB and NPIC in address 010H, bits 2-0) are provided for selecting one or more of the TUG-3 NPIs. The three control bits are enabled when the MOD1 and MOD0 control bits are 11 (TUG-3/VC-4 format). The NPI consists of three bytes, starting with row 1. The table below shows the bit assignment for the first two bytes. Bit Row 1 Row 2 1 1 1 2 0 1 3 0 1 4 1 0 5 0 0 6 0 0 7 1 0 8 1 0
NPI Bit Assignment The third NPI byte is designated as fixed stuff and is transmitted as zero. The remaining cross-hatched bytes in the first two columns of the TUG-3 are tristated on the add bus. When a 1 is written to control bit NULLZ in address 013H, bit 3 and the NPI feature is enabled (i.e., NPIA, NPIB or NPIC is a 1) the bytes following the NPI bytes are transmitted as zeros. When the NULLZ bit is a 0, the bytes following the NPI bytes are tristated.
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E1 LOOPBACK CAPABILITY
QE1M TXC-04252
The QE1M provides two types of E1 loopbacks, called facility and line loopbacks (i.e., at the facility side and at the line side, as illustrated in 20). In 20, the E1 Transmit Data and Clock goes into the QE1M, while the E1 Receive Data and Clock comes out of the QE1M. Facility loopback for port n, enabled when a 1 is written to control bit FnLBK, directs the incoming E1 Transmit Data and Clock to the outgoing Receive Data and Clock signal. Line loopback for port n, enabled when a 1 is written to control bit LnLBK, routes the outgoing E1 Receive Data and Clock signal (instead of the incoming E1 Transmit Data and Clock) to the SDH/SONET transmitter.
FnLBK BYPASn From Desynchronizer 0 1 ANAnEN ANAnTx Facility Loopback Line Loopback E1 LINE PRBS Analyzer REC NRC ANAnOOL 1 HDB3 Coder 0
NRZ Rail
1 0
Receive Data & Clock (NRZ, Rail)
XMIT NRZ 0 To Synchronizer 1 PRBS Generator
0 1
NRZ NRZ
HDB3 Coder
1 0 Transmit Data & Clock (NRZ, Rail)
LnLBK BYPASn
PRBSnEN
Clock
Figure 20. Facility and Line Loopbacks
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QE1M TXC-04252
DATA SHEET
PRBS PATTERN GENERATOR AND ANALYZER Each port has a data generator and analyzer for 215-1 PRBS patterns, as illustrated in 20. The PRBS generator is enabled when a 1 is written to control bit PRBSnEN. The PRBS pattern will be synchronous to the clock driving the HDB3 decoder. When a 1 is written to ANAnEN control bit, the PRBS analyzer is enabled. When control bit ANAnTx is 0, the analyzer will sample the receive NRZ clock and data (REC NRZ) signals. When the control bit ANAnTx is 1, the internal transmit NRZ clock and data signals (XMIT NRZ) will be sampled by the analyzer.
RESETS The Quad E1 Mapper has several reset options. These include a full hardware and software device reset, partial software resets, and counter software resets. All of the software reset bits are self-clearing (i.e., they do not require 0 to be written to a register location after the reset is applied by setting the bit to 1). Note that the self-clearing function requires the presence of the clock signal provided to the EXTCK lead (lead 138 or D10). Upon power-up, when the RESET bit (address 015H, bit 7) is written with a 1, or an active low signal is placed on the RESET lead (lead 155 or C5), the add bus data and the port E1 interfaces are forced to a high impedance state until the device is initialized. The control bits AAHZE and BAHZE (address 010H, bits 5 and 4) must be written with zeros to enable the add bus interfaces. The RnEN control bits must be programmed to 1 to activate the line interfaces. In addition, the AAIND, BAIND, AADD and BADD leads are forced off. All performance counters are reset, and the alarms (except AnLOP and BnLOP) are reset. The control bits (except those shaded in the Memory Map) are also forced to zero, and the various FIFOs are re-initialized. The shaded bits are contained in the Data RAM, and these can be initialized by writing a 1 to INITSP (see Memory Map Descriptions, address 015H, bit 0). A hardware reset can only be applied after the clocks are stable, and must be present for a minimum duration of 150 ns. Writing a 1 to the RnSETS software reset control bit for any of the ports resets the port n performance counters, re-initializes the FIFO, and clears the alarms, except the AnLOP and BnLOP alarms, which will set for port n. The loss of pointer alarms will recover when a valid pointer is received. The control bits will not be reset. Writing a 1 to the RnSETC counter reset control bit for any of the ports reset the performance counters for that port. This feature allows the performance measurements to start at the same time for a port. Writing a 1 to control bit RESTAB (address 015H, bit 6) resets the alarms for the A bus and for LEXTC (i.e., addresses 022H to 025H). Writing a 1 to control bit RESTBB (address 015H, bit 5) resets the alarms for the B bus and the SPOT alarms (i.e., addresses 026H to 028H). Note that a hardware reset will automatically trigger all the software reset bits. Software reset bit RESET will trigger all RnSETS, all RnSETC, RESTAB and RESTBB automatically. A RnSETS will also automatically trigger a RnSETC.
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START-UP PROCEDURE
QE1M TXC-04252
The following procedure should be followed to start up the QE1M in a known good state from initial power-on, or from a hardware or software reset. Initial power-on: From a hardware reset: From a software reset: (1) Power up Device (2) Apply Hardware Reset (lead 155 or C5) (3) Load SPOT microcode (see flowchart in Figure 26) (4) Apply Software Reset (RESET=1; register 0x015 = 0x80) (5) Initialize Data RAM (INITSP=1; register 0x015 = 0x01) (6) Load all Control Registers for user specific operation (7) Clear any alarms that may have been latched, by generating the following resets: - RESTAB and RESTBB (register 0x015 = 0x60) - R1SETS (register 0x052 = 0x80) - R2SETS (register 0x082 = 0x80) - R3SETS (register 0x0B2 = 0x80) - R4SETS (register 0x0E2 = 0x80) (8) Clear AnLOP and BnLOP by reading the corresponding Port Status Registers: - Clear A1LOP (read register 0x030) - Clear A2LOP (read register 0x060) - Clear A3LOP (read register 0x090) - Clear A4LOP (read register 0x0C0) - Clear B1LOP (read register 0x03A) - Clear B2LOP (read register 0x06A) - Clear B3LOP (read register 0x09A) - Clear B4LOP (read register 0x0CA) (start from step 1) (start from step 2) (start from step 4)
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QE1M TXC-04252
DATA SHEET
POINTER LEAK RATE CALCULATIONS
10 SEC
Set FIFO Leak Rate to 04 Hex (Note 3)
Measure 1 Second, add to C (Note 4)
10 SEC
Calculate FIFO Leak Rate (Note 5)
Start AIS, LOP LOS, NDF or RESET Set FIFO Leak Rate (Note 6)
Subt Oldest Add Newest (Note 7)
Measure 1 Second (Note 6)
Notes: 1. The procedure described in Notes 2 through 8 below must be performed independently for each of the four ports of the QE1M device. 2. The procedure shown in the diagram above uses a ten-second sliding window with a resolution of one second. 3. The initial FIFO Leak Rate Register value (in memory map address 049H, 079H, 0A9H or 0D9H) must first be set to 04 Hex. 4. Measure ten consecutive one-second samples from the Positive and Negative Stuff Counters being used. Store all ten difference values, i.e., S1 = POS STUFF COUNT1 - NEG STUFF COUNT1, S2 = POS STUFF COUNT2 - NEG STUFF COUNT2, and so on through S10 = POS STUFF COUNT10 - NEG STUFF COUNT10. There are eight pairs of stuff counters in the QE1M; care should be taken to use the pair appropriate to the programmed configuration of the device. The counters are located at addresses 032H, 062H, 092H, 0C2H (A side) and 03CH, 06CH, 09CH, 0CCH (B side). 5. Calculate the leak rate (L.R.) using the following equation: L.R. = Hex[ Int [ 280 / C ] ], where C = ABS [ S1 + S2 + ... + S10 ]. Then, if L.R. < 4, let L.R. = 4, or if L.R. > 255, let L.R. = 255. 6. Set the FIFO Leak Rate Register (address 049H, 079H, 0A9H or 0D9H) with the value between 4 and 255 calculated above, then take another one-second sample (e.g., S11). 7. Recalculate the value of 'C' by subtracting the oldest sample and adding the newest, and calculate a new leak rate, as described in Note 5 (e.g., using S2 through S11). 8. Continue to repeat the steps described in Notes 5, 6 and 7 until AIS, LOP, LOS or NDF is received or until you reset the QE1M.
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DATA SHEET
JITTER MEASUREMENTS Equipment used in QE1M jitter measurements: * * * Hewlett-Packard Digital Transmission Analyzer:HP-3784A Anritsu Digital Transmission Analyzer:ME520B Anritsu STM/SONET Analyzer:MP1560A
QE1M TXC-04252
The following table lists the filter characteristics defined by specification: Specifications G.703 Interface 2048 kbit/s Filter Used f1 (High Pass) 20 Hz 20 dB/decade HP1 Filter Characteristics f3 (High Pass) 18 kHz 20 dB/decade HP2 f4 (Low Pass) 100 kHz -20 dB/decade LP
Jitter Tolerance Test The jitter tolerance test is performed by inserting various jitter levels at selected frequencies into the 2.048 Mbit/s line input of the QE1M, as shown in the table below and Figure 21. Data is looped back at the SDH/SONET interface and dropped by the same QE1M device. The measured value is the maximum input jitter that the QE1M can tolerate at its input without generating bit errors in the loopback path. Figure 22 is a plot of the measured data listed in the table.
Input Jitter Frequency 10 Hz 2.4 kHz 18 kHz 100 kHz
Requirement >1.5 UI > 1.5 UI > 0.2 UI > 0.2 UI
Maximum Input Jitter Tolerated (UI-PP) 10 UI 2.3 UI 2.2 UI 1.0 UI
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DATA SHEET
Figure 21. Jitter Tolerance and Jitter Test Arrangements
Receiver External Loopback 155 Mbit/s QE1M Test Fixture 2.048 Mbit/s E1 Interface Transmitter PDH Digital Transmission Analyzer
Figure 22. Jitter Tolerance Measurements
JITTER TOLERANCE
10
UI
1
Measured
Required (min)
0.1 10
100
1000
10000
100000
Input Jitter Frequency, Hz
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Jitter Transfer Test
QE1M TXC-04252
A fixed jitter level of 0.5 UI is inserted into the transmitted E1 signal. The jitter value measured is achieved using the HP1/LP filter in the PDH receiver. The jitter transfer measurements are provided in the following table and Figure 23. Input Jitter Frequency 10 Hz 50 Hz 100 Hz 200 Hz 600 Hz 1000 Hz Unit Interval 1.0 UI 1.0 UI 1.0 UI 1.0 UI 1.0 UI 1.0 UI f1-f4 (HP1/LP) Filter Used Jitter Transfer (UI - PP, max) 0.172 UI 0.127 UI 0.117 UI 0.099 UI 0.076 UI 0.075 UI
10.0
1.0 Input M e as ured 0.1
UI 0.0 10 100 Input Jitte r Fre que ncy 1000
Figure 23. Jitter Transfer Measurements
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QE1M TXC-04252
Mapping Jitter Measurement
DATA SHEET
The following table lists the mapping jitter measurements, which are made with a SDH/SONET Analyzer replacing the 155 Mbit/s loopback in Figure 21.
G.703 Interface 2048 kbit/s
Filter Characteristics f1-f4 (HP1/LP) f3-f4 (HP2/LP)
Maximum Output Jitter (UI-PP) Requirement (Note 1) < 0.075 UI Measured Value 0.032 0.024
Note 1: These values are for further study.
Combined Jitter Measurement The following table lists the combined jitter measurements.
Pointer Test Sequence
Filter
Leak Rate (Hex) (Note 1) 01H 12H 12H 16H
Maximum Output Jitter (UI - PP) Requirement 0.4 (Note 2) Measured 0.019 0.169 0.169 0.164 0.075 (Note 2) 0.009 0.009 0.009 0.009
1 2 3 4 1 2 3 4
Single Pointers of Opposite Polarity Regular Pointers Plus One Double Pointer Regular Pointers with One Missing Pointer Double Pointers of Opposite Polarity Single Pointers of Opposite Polarity Regular Pointers Plus One Double Pointer Regular Pointers with One Missing Pointer Double Pointers of Opposite Polarity
f1-f4 (HP1/LP)
f3-f4 (HP2/LP)
01H 12H 12H 16H
Note 1: These values are written into the Desynchronizer Pointer Leak Rate Register for mapper port n (register address 049, 079, 0A9, 0D9 hex, for n = 1 - 4). Note 2: The limit corresponds to the pointer sequences shown in Figure 24 for Standard Pointer Test Sequences, (T1 10 s, T2 > 0.75 s, T3 = 30 ms). The T3 value was constrained by test equipment limitations.
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Figure 24. Standard Pointer Test Sequences
QE1M TXC-04252
T1 Single Pointers of Opposite Polarity T2 T3
Regular Pointers plus one Double Poiner T2
Regular Pointers with one Missing Value T3 T1 Double Pointers of Opposite Polarity
T3
(Ref: ITU-T G.783, Fig. 6-2)
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QE1M TXC-04252
INTERNAL SPOT PROCESSOR
DATA SHEET
The internal SPOT processor of the QE1M device is a SONET Processor for Overhead Termination. The purpose of the SPOT processor is to relieve the device's internal logic of the need to support relatively slow functions like performance monitoring and alarm handling. The utility of this feature will grow as communications standards require tighter control of data flow and network management. In addition, as boards become more densely populated with VLSI components, the availability of the SPOT processor will help by reducing the requirement for external components and the workload of the main processor (and the software engineers who program it). The SPOT processor is a programmable core which adheres to Reduced Instruction Set Computer (RISC) principles. It executes one instruction per clock cycle. Instructions are simple, performing data movement, basic arithmetic functions (8-bit integer operations, but no multiply/divide) and program control. The executable device microcode required for operation of the SPOT processor and associated descriptive text is available via the QE1M selection option of the Product Finder on the home page of the TranSwitch Internet World Wide Web site at www.transwitch.com, where the files are provided in ZIP format. The SPOT processor is designed to run at 29.16 MHz. This clock is internally derived from the 58.32 MHz desynchronizer clock input (EXTCK). The Instruction RAM (I-RAM) has 2048 words of 16 bits while the Data RAM (D-RAM) has 2048 words of 8 bits. The SPOT processor has access to the Microprocessor Interface and the Add/Drop Engines of the QE1M via an 8-bit data bus, as shown in Figure 25. The SPOT processor is event-driven, with each client independently and asynchronously requesting service. These maskable requests are surveyed by a task queue and prioritized by function (Add, Drop, Line). When idle, the SPOT processor polls the task queue to identify the next client to be serviced. This results in a call to the appropriate subroutine(s). During each subroutine, the SPOT processor may transfer data to/from the Add/Drop Engines or the Microprocessor Interface. The SPOT processor will make decisions regarding control/status and update any necessary counters and other Data RAM locations. The subroutine is terminated by returning to the idle loop, and the cycle is then repeated. The E1 data paths (i.e., for the Add/Drop Engines) are implemented in free-running hardware, and are therefore not dependent on the SPOT processor. The Data RAM contains important information about the status of the E1 channels. Performance counters, J2 messages, etc., are all stored there. The external microprocessor is granted access to the internal Data RAM when addressing the appropriate locations. Since RAM access is arbitrated, the grant will not be immediate, and the RDY/DTACK signal is de-asserted until the requested data becomes available. Since the SPOT processor is effectively a very large state machine, it could enter an unforeseen state (e.g., due to a software bug or RAM corruption) which prevents it from servicing all requests in a timely manner. Although the data path is not interrupted, the path overhead bytes may not be correctly processed under these conditions. Two status bits have been provided to detect critical errors which are indications of this status: Parity Error (PERR) in bit 4 of addresses 028H and 029H indicates that a parity error has occurred in reading the Instruction RAM. Watchdog Timer Expired (WDTEXP) in bit 6 of addresses 028H and 029H indicates that the SPOT processor may be unable to service all requests in a timely manner. Some possible causes for this condition are excessive microprocessor accesses, a SPOT processor clock that is running too slowly, or a software bug.
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QE1M TXC-04252
Upon power-up or hardware reset, the contents of the Instruction RAM are assumed to be invalid and execution of the SPOT program is internally disabled. Before the SPOT processor can begin processing, the microprocessor must reprogram the Instruction RAM, using the instructions described in the following table, by performing the procedure described in the flowchart in Figure 26. Table 1: Reprogram Functions (valid only when control bit RPSPOT at bit 7 in address 007H is a 1) Function wrPC rdPC0 rdPC1 IRAMwr IRAMrd Direction write read read write read Microprocessor Interface Address 102H 102H 103H 100H 100H Description IRAMptr <== SPOTPCLD(10-0) read IRAMptr[7:0] read IRAMptr[10:8] *IRAMptr++ <== data data <== *IRAMptr++
The 11-bit SPOT PC Load register SPOTPCLD at address 007H bits 2-0 and address 006H bits 7-0 is first initialized. This is an offset address into the Instruction RAM. It may not be necessary always to write/read the entire program, but for normal operation this register should be set to 000H. In order to access the Instruction RAM, set to 1 the Reprogram SPOT control bit RPSPOT at bit 7 in address 007H. At this time the Data RAM is off-line (i.e., it is inaccessible to the microprocessor), but all register-based locations are still available. SPOT program execution is disabled when RPSPOT is a 1. Function "wrPC" causes the Instruction RAM word pointer to be loaded from the SPOT PC Load register. The SPOT processor automatically increments the Instruction RAM word pointer, which allows the microprocessor to write all instructions to one address (100H). Since the length of the Instruction RAM is 2048 16-bit words, 4096 IRAM 8-bit write functions ("IRAMwr") are required to program the SPOT processor completely. TranSwitch provides the 4096 bytes of code that will implement the features mentioned in this document. It is recommended, but not required, that the writes to the Instruction RAM should be verified as part of the initialization procedure. As shown in the flowchart, it is necessary only to use the instruction "wrPC" to reload the I-RAM word pointer and then perform 4096 I-RAM read cycles using the same fixed data location (100H) as that used for write (function "IRAMrd"). The programming procedure is completed by setting control bit RPSPOT to 0. At this point, the word pointer is reloaded and execution of the SPOT processor program execution is enabled. It is important to set control bit INITSP at address 015H, bit 0 to 1 at some time after programming the SPOT processor. This will cause the SPOT processor to execute an initialization subroutine from the Instruction RAM that will initialize the Data RAM and reset its general purpose registers to allow other subroutines to begin running from a known state.
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DATA SHEET
Figure 25. Schematic Diagram of QE1M Showing SPOT Processor Interfaces
SDH/SONET SIDE Drop[A]
LINE SIDE DROP Engine
Rx Port
Drop[B]
arbiter
Inst. RAM
Data RAM
RAM I/F Control/Status
P Input/Output
SPOT
P Interface
ADD Engine Add[A]
Tx Port
Add[B]
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Figure 26. Recommended Implementation Flowchart for Reprogramming the SPOT Processor
Initialize LATEN = 0 HDWIE = 1 SPTMSK = 1 SPOTPCLD=000H RPSPOT = 1
wrPC 102H = 00H
Download
Write next byte No more data? n 100H = data
y
wrPC 102H = 00H
Verify
Read next byte No more data? n data = 100H
y
Wrap Up RPSPOT = 0
Note: RESTSP must be 0 during reprogramming.
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QE1M TXC-04252
BOUNDARY SCAN Introduction
DATA SHEET
The Boundary Scan Interface Block provides a five-lead Test Access Port (TAP) that conforms to the IEEE 1149.1 standard. This standard provides external boundary scan functions to read and write the external Input/Output leads from the TAP for board and component test. The IEEE 1149.1 standard defines the requirements of a boundary scan architecture that has been specified by the IEEE Joint Test Action Group (JTAG). Boundary scan is a specialized scan architecture that provides observability and controllability for the interface leads of the device. As shown in Figure 27, one cell of a boundary scan register is assigned to each input or output lead to be observed or tested (bidirectional leads may have two cells). The boundary scan capability is based on a Test Access Port (TAP) controller, instruction and bypass registers, and a boundary scan register bordering the input and output leads. The boundary scan test bus interface consists of four input signals (Test Clock (TCK), Test Mode Select (TMS), Test Data Input (TDI) and Test Reset (TRS)) and a Test Data Output (TDO) output signal. Boundary scan signal timing is shown in 17. The TAP controller receives external control information via a Test Clock (TCK) signal and a Test Mode Select (TMS) signal, and sends control signals to the internal scan paths. Detailed information on the operation of this state machine can be found in the IEEE 1149.1 standard. The serial scan path architecture consists of an instruction register, a boundary scan register and a bypass register. These three serial registers are connected in parallel between the Test Data Input (TDI) and Test Data Output (TDO) signals, as shown in Figure 27. The boundary scan function can be reset and disabled by holding lead TRS low. When boundary scan testing is not being performed the boundary scan register is transparent, allowing the input and output signals to pass to and from the QE1M device's internal logic. During boundary scan testing, the boundary scan register may disable the normal flow of input and output signals to allow the device to be controlled and observed via scan operations. Boundary Scan Operation The maximum frequency the QE1M device will support for boundary scan is 10 MHz. The timing diagrams for the boundary scan interface leads are shown in 17. The instruction register contains three bits. The QE1M device performs the following three boundary scan test instructions: The EXTEST test instruction (000) provides the ability to test the connectivity of the QE1M device to external circuitry. The SAMPLE test instruction (010) provides the ability to examine the boundary scan register contents without interfering with device operation. The BYPASS test instruction (111) provides the ability to bypass the QE1M boundary scan and instruction registers. Boundary Scan Reset Specific control of the TRS lead is required in order to ensure that the boundary scan logic does not interfere with normal device operation. This lead must either be held low, asserted low, or asserted low then high (pulsed low), to asynchronously reset the Test Access Port (TAP) controller during power-up of the QE1M. If boundary scan testing is to be performed and the lead is held low, then a pull-down resistor value should be chosen which will allow the tester to drive this lead high, but still meet the VIL requirements listed in the `Input, Output and Input/Output Parameters' section of this Data Sheet for worst case leakage currents of all devices sharing this pull-down resistor.
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DATA SHEET
Figure 27. Boundary Scan Schematic
QE1M TXC-04252
Boundary Scan Register
CORE LOGIC OF QE1M DEVICE
Signal input and output leads (shown for PQFP; PBGA package has solder ball leads on bottom surface).
Instruction Register Bypass Register TAP Controller
TDI
3 Controls IN OUT Boundary Scan Serial Test Data
TDO
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QE1M TXC-04252
Boundary Scan Chain
DATA SHEET
There are 159 scan cells in the boundary scan chain associated with QE1M core logic functions. Bidirectional signals require two scan cells. Additional scan cells are used for direction control as needed. A boundary scan description language (BSDL) source file is available via the Products page of the TranSwitch Internet World Wide Web site at www.transwitch.com. The following table shows the listed order of the scan cells and their function. Scan Cell No. I/O Lead No. PQFP Output 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Input Input Input Input Input Input Output (2-state) Output (2-state) Input Input Input Input Output (3-state) Output (3-state) --Output (3-state) --Output (3-state) Output (3-state) --Output (3-state) --Input Input 37 33 32 31 30 28 26 24 23 21 20 19 18 16 15 --14 --12 11 --10 --8 7 D4 D1 E1 E4 E3 F1 PBGA P1 M3 L2 L1 L4 K2 K3 J2 J3 H1 G4 G1 G2 F4 F3 TDO ADSPE ADC1J1V1 AASPE AAC1J1V1 AACLK ADCLK ADIND AAIND TPI1 TNI1 TCI1 QUIET1 RPO1 RNO1 SCAN Chain output Symbol Comments
RN1_OE
RCO1
When high, lead 15 or F3 is tristated.
RCP1_OE
RPO3 RNO3
When high, leads 14 or F1 and 16 or F4 are tristated.
RN3_OE
RCO3
When high, lead 11 or E3 is tristated.
RCP3_OE
TPI3 TNI3
When high, leads 10 or E1 and 12 or E4 are tristated.
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DATA SHEET
QE1M TXC-04252
Scan Cell No. 24 25 26 27 28 29
I/O
Lead No. PQFP PBGA D3 D2 C1 B1 C3 C3
Symbol
Comments
Input Input Input Input Input Output (3-state)
6 5 3 2 1 1
TCI3 QUIET3 MUX MOTO UPA10 (A10) (in) UPA10 (A10) (out) UPA9 (A9) (in) UPA9 (A9) (out) UPA8 (A8) (in) UPA8 (A8) (out) A7 (in) A7 (out) ABUST Although they are normally inputs, all address leads can be driven internally by the SPOT processor in test mode.
30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Input Output (3-state) Input Output (3-state) Input Output (3-state) Input --Input Output (3-state) Input Input Output (3-state) Output (3-state) --Input Input Input Input
160 160 159 159 158 158 157 --156 156 155 153 153 152 --150 149 148 147
B2 B2 A2 A2 A3 A3 A4
UPA_OE2
B5 B5 C5 C6 C6 D6 A6 (in) A6 (out) RESET A5 (in) A5 (out) INT/IRQ
When high, leads 158 or A3, 159 or A2, 160 or B2 and 1 or C3 are tristated.
INT_OE
B7 A7 C7 D7 INTSH ALE WR (WR/LDS) RD (RD / RD/WR)
When high, lead 152 or D6 is tristated.
Used only in MUX mode.
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QE1M TXC-04252
DATA SHEET
Scan Cell No. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
I/O
Lead No. PQFP PBGA
Symbol
Comments
--Input --Input --Input Output (3-state) Input Output (3-state) Input Output (3-state) Input Output (3-state) Input --Input --Input Output (3-state) Input Output (3-state) Input Output (3-state) Input
--146 --145 --144 144 143 143 141 141 140 140 138 --136 --135 135 133 133 132 132 130 B10 B10 D11 D11 C11 C11 C12 A10 C8 C8 D8 D8 C9 C9 B9 B9 D10 A8 B8
UPA_OE1
SEL
When high, leads 144 or C8, 153 or C6 and 156 or B5 are tristated.
UPA_OE0
TEST
When high, leads 135 or B10, 140 or B9, 141 or C9 and 143 or D8 are tristated.
UPD_OE3
A4 (in) A4 (out) A3 (in) A3 (out) A2 (in) A2 (out) A1 (in) A1 (out) EXTCK
When high, leads 132 or C11 and 133 or D11 are tristated.
UPD_OE2
HIGHZ
When high, leads 129 or A12 and 130 or C12 are tristated.
UPD_OE1
A0 (in) A0 (out) UPAD7 (D7) (in) UPAD7 (D7) (out) UPAD6 (D6) (in) UPAD6 (D6) (out) UPAD5 (D5) (in)
When high, leads 126 or A13 and 128 or B12 are tristated.
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QE1M TXC-04252
Scan Cell No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95
I/O
Lead No. PQFP PBGA C12 A12 A12 B12 B12 A13 A13 C13 C13 B13 B13 A15
Symbol
Comments
Output (3-state) Input Output (3-state) Input Output (3-state) Input Output (3-state) Input Output (3-state) Input Output (3-state) Output (3-state) --Input --Input Input Input Input Output (3-state) Output (3-state) --Output (3-state)
130 129 129 128 128 126 126 125 125 124 124 122 --121 --119 118 117 116 114 113 --112
UPAD5 (D5) (out) UPAD4 (D4) (in) UPAD4 (D4) (out) UPAD3 (D3) (in) UPAD3 (D3) (out) UPAD2 (D2) (in) UPAD2 (D2) (out) UPAD1 (D1) (in) UPAD1 (D1) (out) UPAD0 (D0) (in) UPAD0 (D0) (out) RDY/DTACK
RDY_OE
C14 SPARE2
When high, lead 122 or A15 is tristated.
UPD_OE0
B15 A16 C15 C16 D14 E15 QUIET4 TCI4 TNI4 TPI4 RCO4 RNO4
When high, leads 124 or B13 and 125 or C13 are tristated.
RN4_OE
E14 RPO4
When high, lead 113 or E15 is tristated.
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QE1M TXC-04252
DATA SHEET
Scan Cell No. 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125
I/O
Lead No. PQFP PBGA
Symbol
Comments
--Output (3-state) Output (3-state) --Output (3-state) --Input Input Input Input Output (2-state) Output (2-state) Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output (2-state) Output (3-state)
--111 110 --109 --107 106 105 104 102 101 99 98 96 95 94 93 91 90 89 88 87 85 84 83 82 80 78 77 G16 G14 G13 H15 J13 J14 K14 K16 L13 L14 L16 L15 M14 M16 M15 N13 N16 P16 P15 R16 P14 R15 R14 T14 F14 E13 F16
RCP4_OE
RCO2 RNO2
When high, leads 112 or E14 and 114 or D14 are tristated.
RN2_OE
RPO2
When high, lead 110 or F16 is tristated.
RCP2_OE
QUIET2 TCI2 TNI2 TPI2 BAIND BDIND BDCLK BACLK BAC1J1V1 BASPE BDC1J1V1 BDSPE BDPAR BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 SPARE1 BADD BAPAR
When high, leads 109 or F14 and 111 or E13 are tristated.
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QE1M TXC-04252
Scan Cell No. 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152
I/O
Lead No. PQFP PBGA T13
Symbol
Comments
Output (3-state) --Output (3-state) Output (3-state) Output (3-state) --Output (3-state) Output (3-state) Output (3-state) --Output (3-state) Output (3-state) Output (3-state) --Output (3-state) Output (3-state) Output (3-state) --Output (3-state) Output (3-state) Output (3-state) Output (3-state) --Output (2-state) Input Input Input
76 --75 73 72 --71 69 68 --67 65 64 --63 62 60 --59 58 56 55 --54 52 51 50
BA7
BA_OE2
R13 R12 T12 BA6 BA5 BA4
When high, leads 75 or R13, 76 or T13 and 77 or T14 are tristated.
BA_OE1
P12 T11 P11 BA3 BA2 BA1
When high, leads 71 or P12, 72 or T12 and 73 or R12 are tristated.
BA_OE0
N11 T10 P10 BA0 AA0 AA1
When high, leads 67 or N11, 68 or P11 and 69 or T11 are tristated.
AA_OE0
N10 R9 N9 AA2 AA3 AA4
When high, leads 63 or N10, 64 or P10 and 65 or T10 are tristated.
AA_OE1
N8 P8 P7 T7 AA5 AA6 AA7 AAPAR
When high, leads 59 or N8, 60 or N9 and 62 or R9 are tristated.
AA_OE2
R7 N6 P6 T6 AADD AD0 AD1 AD2
When high, leads 55 or T7, 56 or P7 and 58 or P8 tristated.
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QE1M TXC-04252
DATA SHEET
Scan Cell No. 153 154 155 156 157 158
I/O
Lead No. PQFP PBGA N5 P5 T5 P4 R4 T3 R1
Symbol
Comments
Input Input Input Input Input Input Input
48 47 46 44 43 42 38
AD3 AD4 AD5 AD6 AD7 ADPAR TDI SCAN chain input
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DATA SHEET
MULTIPLEX FORMAT AND MAPPING INFORMATION STS-1 VT2 (2.048 Mbit/s) Multiplex Format Mapping
QE1M TXC-04252
The following diagram and table illustrate the mapping of the 21 VT2s into an STS-1 SPE. Column 1 is assigned to carry the path overhead bytes.
VT2
4 COLUMNS
1 2 3
1 5
2
3
4
36
36
1 J1 B3 C2 VT 2 G1 # F2 1 H4 Z3 Z4 Z5 2 23 VT 2 # 2 VT 2 # 21 VT 2 # 1 VT 2 # 2 R R R R R R R R R 30 VT 2 # 21 VT 2 # 1 VT 2 # 2 R R R R R R R R 45 R 59 67 87 VT 2 # 21 VT 2 # 1 VT 2 # 21
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DATA SHEET
STS-1 Mapping (2.048 Mbit/s) VT# RTUNn, TTUNn Locations 04CH, 04DH Port 1 0ACH, 0ADH Port 3 07CH, 07DH Port 2 0DCH, 0DDH Port 4 6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 0 1 1 1 1 3 0 0 1 1 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 1 1 2 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 No VT Selected 2, 23, 45, 67 3, 24, 46, 68 4, 25, 47, 69 5, 26, 48, 70 6, 27, 49, 71 7, 28, 50, 72 8, 29, 51, 73 9, 31, 52, 74 10, 32, 53, 75 11, 33, 54, 76 12, 34, 55, 77 13, 35, 56, 78 14, 36, 57, 79 15, 37, 58, 80 16, 38, 60, 81 17, 39, 61, 82 18, 40, 62, 83 19, 41, 63, 84 20, 42, 64, 85 21, 43, 65, 86 22, 44, 66, 87 VT2 Column Numbers*
* Note: Columns 30 and 59 carry fixed stuff bytes. Column 1 is assigned for the POH bytes.
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STS-3/AU-3 VT2/TU-12 (2.048 Mbit/s) Multiplex Format Mapping
QE1M TXC-04252
The following diagram and table illustrate the mapping of the 63 VT2/TU-12s into an STS-3/AU-3 SPE. Each STS-3 carries three STS-1s. Column 1 in each STS-1/AU-3 is assigned to carry the path overhead bytes.
VT2
4 COLUMNS
1 2 3
36 BYTES
1 5
2
3
4
36
35 36
1 J1 B3 C2 VT 2 G1 # F2 1 H4 Z3 Z4 Z5
23
29 30 R R VT R 2 #R 7R R R R R
44 45
59 60 R R
66 67
87
1 J1 B3 C2 VT 2 G1 # F2 22 H4 Z3 Z4 Z5
87
1 J1 B3 C2 VT 2 G1 # F2 43 H4 Z3 Z4 Z5
87
VT 2 # 1
VT 2 # 21
VT 2 # 1
R VT 2 R# R 15 R R R R
VT VT 22 ## 21 1
VT 2 # 21
VT 2 # 23
VT 2 # 42
VT 2 # 44
VT 2 # 63
1
STS-3/AU-3 SPE
261
Note: Columns 88, 89, 90, 175, 176 and 177 are fixed stuff.
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DATA SHEET
STS-3/AU-3 Mapping (2.048 Mbit/s)
RTUNn, TTUNn 04CH, 04DH Port 1 07CH, 07DH Port 2 0ACH, 0ADH Port 3 0DCH, 0DDH Port 4 Registers 6543210 0000000 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 0100101 0101001 0101101 0110001 0110101 0111001 0111101 0100110 0101010 0101110 0110010 0110110 0111010 0111110 0100111 0101011 0101111 0110011 0110111 0111011 0111111 4, 67, 133, 199 7, 70, 136, 202 10, 73, 139, 205 13, 76, 142, 208 16, 79, 145, 211 19, 82, 148, 214 22, 85, 151, 217 25, 91, 154, 220 28, 94, 157, 223 31, 97, 160, 226 34, 100, 163, 229 37, 103, 166, 232 40, 106, 169, 235 43, 109, 172, 238 46, 112, 178, 241 49, 115, 181, 244 52, 118, 184, 247 55, 121, 187, 250 58, 124, 190, 253 61, 127, 193, 256 64, 130, 196, 259 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 1000101 1001001 1001101 1010001 1010101 1011001 1011101 1000110 1001010 1001110 1010010 1010110 1011010 1011110 1000111 1001011 1001111 1010011 1010111 1011011 1011111 RTUNn, TTUNn 04CH, 04DH Port 1 07CH, 07DH Port 2 0ACH, 0ADH Port 3 0DCH, 0DDH Port 4 Registers 6543210 RTUNn, TTUNn 04CH, 04DH Port 1 07CH, 07DH Port 2 0ACH, 0ADH Port 3 0DCH, 0DDH Port 4 Registers 6543210
TU/ VT #
STS-3/AU-3 Column Numbers*
TU/ VT #
STS-3/AU-3 Column Numbers*
TU/ VT #
STS-3/AU-3 Column Numbers*
No TU/VT Selected 5, 68, 134, 200 8, 71, 137, 203 11, 74, 140, 206 14, 77, 143, 209 17, 80, 146, 212 20, 83, 149, 215 23, 86, 152, 218 26, 92, 155, 221 29, 95, 158, 224 32, 98, 161, 227 35, 101, 164, 230 38, 104, 167, 233 41, 107, 170, 236 44, 110, 173, 239 47, 113, 179, 242 50, 116, 182, 245 53, 119, 185, 248 56, 122, 188, 251 59, 125, 191, 254 62, 128, 194, 257 65, 131, 197, 260 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 1100101 1101001 1101101 1110001 1110101 1111001 1111101 1100110 1101010 1101110 1110010 1110110 1111010 1111110 1100111 1101011 1101111 1110011 1110111 1111011 1111111 6, 69, 135, 201 9, 72, 138, 204 12, 75, 141, 207 15, 78, 144, 210 18, 81, 147, 213 21, 84, 150, 216 24, 87, 153, 219 27, 93, 156, 222 30, 96, 159, 225 33, 99, 162, 228 36, 102, 165, 231 39, 105, 168, 234 42, 108, 171, 237 45, 111, 174, 240 48, 114, 180, 243 51, 117, 183, 246 54, 120, 186, 249 57, 123, 189, 252 60, 126, 192, 255 63, 129, 195, 258 66, 132, 198, 261
STS-1 #1, AU-3 A
STS-1 #2, AU-3 B
STS-1 #3, AU-3 C
* Note: Columns 88, 89, 90, 175, 176 and 177 are fixed stuff.
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STM-1/VC-4 TU-12 (2048 kbit/s) Multiplex Format Mapping
QE1M TXC-04252
The following diagram and table illustrate the mapping of the 63 TU-12s into an STM-1/VC-4. The QE1M provides control bits for enabling the Null Pointer Indicators (NPIs) for the columns indicated.
4 COLUMNS
1 2 3
1 5
2
3
4
TU-12 #1
36
36
1 2 3 TUG-2 #1
1 2 3
1 2 3
1 2 3
1 N P I
3
24
45
66
86
1 N P I
86
1 N P I
86
1
7
1
71
7
1
7
8
14
15
21
TUG-3A
TUG-3B
TUG-3C
VC-4 P O H
1
STM-1/VC-4
261
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DATA SHEET
STM-1 VC-4 Mode (2048 kbit/s)
RTUNn, TTUNn 04CH, 04DH Port 1 07CH, 07DH Port 2 0ACH, 0ADH Port 3 0DCH, 0DDH Port 4 Registers 6543210 0000000 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 0100101 0101001 0101101 0110001 0110101 0111001 0111101 0100110 0101010 0101110 0110010 0110110 0111010 0111110 0100111 0101011 0101111 0110011 0110111 0111011 0111111 10, 73, 136, 199 13, 76, 139, 202 16, 79, 142, 205 19, 82, 145, 208 22, 85, 148, 211 25, 88, 151, 214 28, 91, 154, 217 31, 94, 157, 220 34, 97, 160, 223 37, 100, 163, 226 40, 103, 166, 229 43, 106, 169, 232 46, 109, 172, 235 49, 112, 175, 238 52, 115, 178, 241 55, 118, 181, 244 58, 121, 184, 247 61, 124, 187, 250 64, 127, 190, 253 67, 130, 193, 256 70, 133, 196, 259 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 1000101 1001001 1001101 1010001 1010101 1011001 1011101 1000110 1001010 1001110 1010010 1010110 1011010 1011110 1000111 1001011 1001111 1010011 1010111 1011011 1011111 RTUNn, TTUNn 04CH, 04DH Port 1 07CH, 07DH Port 2 0ACH, 0ADH Port 3 0DCH, 0DDH Port 4 Registers 6543210 RTUNn, TTUNn 04CH, 04DH Port 1 07CH, 07DH Port 2 0ACH, 0ADH Port 3 0DCH, 0DDH Port 4 Registers 6543210
TU #
VC-4 Column Numbers
TU #
VC-4 Column Numbers
TU #
VC-4 Column Numbers
No TU Selected 11, 74, 137, 200 14, 77, 140, 203 17, 80, 143, 206 20, 83, 146, 209 23, 86, 149, 212 26, 89, 152, 215 29, 92, 155, 218 32, 95, 158, 221 35, 98, 161, 224 38, 101, 164, 227 41, 104, 167, 230 44, 107, 170, 233 47, 110, 173, 236 50, 113, 176, 239 53, 116, 179, 242 56, 119, 182, 245 59, 122, 185, 248 62, 125, 188, 251 65, 128, 191, 254 68, 131, 194, 257 71, 134, 197, 260 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 1100101 1101001 1101101 1110001 1110101 1111001 1111101 1100110 1101010 1101110 1110010 1110110 1111010 1111110 1100111 1101011 1101111 1110011 1110111 1111011 1111111 12, 75, 138, 201 15, 78, 141, 204 18, 81, 144, 207 21, 84, 147, 210 24, 87, 150, 213 27, 90, 153, 216 30, 93, 156, 219 33, 96, 159, 222 36, 99, 162, 225 39, 102, 165, 228 42, 105, 168, 231 45, 108, 171, 234 48, 111, 174, 237 51, 114, 177, 240 54, 117, 180, 243 57, 120, 183, 246 60, 123, 186, 249 63, 126, 189, 252 66, 129, 192, 255 69, 132, 195, 258 72, 135, 198, 261
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DATA SHEET MEMORY MAP
QE1M TXC-04252
The QE1M memory map consists of counters and register bit positions which may be accessed by the microprocessor. The memory map segment consists of 7FF (hex) address locations. Address locations in the range 000H - 7FFH that are shown as unused, or are unlisted, must not be accessed by the microprocessor. Unused bit positions within register locations will contain unspecified values when read, unless a 0 or 1 value is indicated in the tables below, or the address can be written by the microprocessor, in which case unused bit positions must always be set to 0. All counters saturate at full count and are cleared when they are read. The common memory map segment consists of the Device ID, Program ID, Internal Processor, Control, Provisioning, Interrupt Indication, and Interrupt Status registers. The A bus segment consists of the A Drop and Add status registers. The B bus segment consists of the B Drop and Add status registers. Each Port n memory map segment (where n = 1-4) consists of the Desynchronizer, Provisioning, Status and Operations registers, and various counters. There are also Port n registers for J2 and N2 (Z6) message segments. Some memory locations, at addresses 032H and above, are shown shaded in the memory map. These locations reside in the 2k x 8 Data RAM of the internal SPOT processor and are not reset by the software or hardware resets but only by INITSP. They are subject to arbitrated access by both the internal SPOT processor and the external microprocessor. An attempt to access any of these locations will toggle the RDY/DTACK output lead to pause the external microprocessor until the location is available for external access. While control bit RPSPOT is set to 1, these locations are assigned to use by the SPOT processor and must not be accessed by the external microprocessor unless they are addresses designated for microprocessor access while the SPOT processor is being reprogrammed (i.e., addresses 100H, 102H and 103H).
DEVICE ID Address Status* (Hex) 000 001 002 003 004 R R R R R Bit 7 1 1 0 Bit 6 1 1 0 Bit 5 0 0 0 Bit 4 1 0 0 Bit 3 0 0 1 0 Bit 2 1 0 0 0 Bit 1 1 0 0 0 Bit 0 1 0 1 1
Revision (Version) Level Mask Level (reads as 0000)
Growth (reads as 0000)
PROGRAM ID Address Status* (Hex) 6BD 6BE 6BF R/W R/W R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Program Revision Checksum/execution flag (PID-CHK) Part 1 of two-part program release number (PGMRV1) Part 2 of two-part program release number (PGMRV2)
* R=Read Only; R(L)=Read Only (Latched); R/W=Read/Write; W=Write Only.
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QE1M TXC-04252
INTERNAL PROCESSOR (SPOT) Address Status* (Hex) 005 006 007 008 R/W R/W R/W R/W RPSPOT Bit 7 Bit 6
DATA SHEET
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TranSwitch Test Register (set to 00H) SPOTPCLD (7 - 0) TranSwitch Test Bits (set to 0000) SPOTPCLD (10 - 8) TranSwitch Test Register (set to 00H)
COMMON REGISTERS - CONTROLS Address Status* (Hex) 010 011 012 013 R/W R/W R/W R/W Bit 7 MOD1 SBTEN ADDI HEAISE Bit 6 MOD0 DRPBT APE DV1SEL Bit 5 AAHZE ABD IPOS DV1REF Bit 4 BAHZE LATEN INEG RDIEN Bit 3 BLOCK TAISE RFIE NULLZ Bit 2 NPIA TCLKI THRSBY DDIND Bit 1 NPIB RAISE DPE UQAE Bit 0 NPIC RCLKI PDDO TOBWZ
COMMON REGISTERS - PROVISIONING (CONTROL) Address Status* (Hex) 014 015 0F1 0F5 R/W W R/W R/W 0 TxB2DIS Bit 7 Bit 6 Bit 5 Bit 4 UEAME 0 0 0 0 Bit 3 SE1AIS V4EN 0 Bit 2 V5AL10 0 0 Bit 1 PTALTE 0 0 Bit 0 HDWIE
INITSP
Unused (set to 000) RESET RESTAB 0 0
RESTBB RESTSP
Unused (set to 000)
0 0
COMMON REGISTERS - INTERRUPT INDICATION Address Status* (Hex) 020 R Bit 7 INT Bit 6 EXTCK Bit 5 ASIDE Bit 4 BSIDE Bit 3 PORT4 Bit 2 PORT3 Bit 1 PORT2 Bit 0 PORT1
COMMON REGISTERS - INTERRUPT MASK Address Status* (Hex) 016 017 018 019 021 R/W R/W R/W R/W R/W Bit 7 0 RPT4A TPORT4 0 Bit 6 0 RPT4B TPORT3 ECKMSK Bit 5 0 RPT3A TPORT2 ASMSK Bit 4 0 RPT3B TPORT1 BSMSK Bit 3 0 RPT2A RFIFO4 P4MSK Bit 2 0 RPT2B RFIFO3 P3MSK Bit 1 0 RPT1A RFIFO2 P2MSK Bit 0 SPTMSK RPT1B RFIFO1 P1MSK
TFIFO4A TFIFO4B TFIFO3A TFIFO3B TFIFO2A TFIFO2B TFIFO1A TFIFO1B
* R=Read Only; R(L)=Read Only (Latched); R/W=Read/Write; W=Write Only.
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DATA SHEET
QE1M TXC-04252
A/B DROP AND ADD BUS REGISTERS - DESYNCHRONIZER AND INTERNAL PROCESSOR (SPOT) STATUS Address Status* (Hex) 022 023 024 025 026 027 028 029 R(L) R R(L) R R(L) R R(L) R Bit 7 ADLOC ADLOC LEXTC LEXTC BDLOC BDLOC Bit 6 AALOC AALOC 0 0 BALOC BALOC Bit 5 ADPAR ADPAR 0 0 BDPAR BDPAR 0 0 Bit 4 0 0 0 0 0 0 PERR PERR Bit 3 0 0 0 0 0 0 0 0 Bit 2 A3UAISI A3UAISI A3DH4E A3DH4E B3UAISI B3UAISI B3DH4E B3DH4E Bit 1 A2UAISI A2UAISI A2DH4E A2DH4E B2UAISI B2UAISI B2DH4E B2DH4E Bit 0 A1UAISI A1UAISI A1DH4E A1DH4E B1UAISI B1UAISI B1DH4E B1DH4E
SPTLOC WDTEXP SPTLOC WDTEXP
DESYNCHRONIZER CONTROL - PORT n Address Port 1, 2, 3, 4
049 079 0A9 0D9
Status* R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Desynchronizer Pointer Leak Rate Register
PROVISIONING (CONTROL) - PORT n Address Port 1, 2, 3, 4
04A 07A 0AA 0DA 04B 07B 0AB 0DB 04C 07C 0AC 0DC 04D 07D 0AD 0DD
Status* R/W R/W R/W R/W
Bit 7 TnSEL1 ADnEN 0 0
Bit 6 TnSEL0 BDnEN
Bit 5 RnSEL AAnEN
Bit 4
Bit 3
Bit 2
Bit 1 RnEN
Bit 0 0
UCHnE USCHnE BYPASn BAnEN Receive TU/VT Select (RTUNn) Transmit TU/VT Select (TTUNn)
ANAnTx ANAnEN PRBSnEN FRDISn
* R=Read Only; R(L)=Read Only (Latched); R/W=Read/Write; W=Write Only.
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QE1M TXC-04252
DATA SHEET
STATUS REGISTERS AND COUNTERS - PORT n (A SIDE) Address Port 1, 2, 3, 4
030 060 090 0C0 031 061 091 0C1 032 062 092 0C2 033 063 093 0C3 034 064 094 0C4 035 065 095 0C5 04E 07E 0AE 0DE 04F 07F 0AF 0DF 036 066 096 0C6 037 067 097 0C7 038 068 098 0C8 039 069 099 0C9 05A 08A 0BA 0EA 05B 08B 0BB 0EB 100 200 300 400 101 201 301 401 102 202 302 402 116 216 316 416
Status* R(L) R R R R R R(L) R R R R R R(L) R R R R R
Bit 7 AnAIS AnAIS
Bit 6 AnLOP AnLOP
Bit 5 AnSIZE AnSIZE
Bit 4 AnNDF AnNDF
Bit 3 AnRDIS AnRDIS
Bit 2 AnRFI AnRFI
Bit 1
Bit 0
AnUNEQ AnSLER AnUNEQ AnSLER
AnPJ Counter AnBIP2 Error Counter AnFEBE Counter Unused AnRDIP AnRDIP AnRDIC AnRDIC Unused (00) Unused (00)
AnNJ Counter
An Rx Label AnJ2LOL AnJ2TIM AnJ2LOL AnJ2TIM Unused Unused Unused (00) Unused (00)
An Receive K4 (Z7) Byte An Receive O-Bits AnTCUQ AnTCAIS AnTCLM AnTCLL AnTCTM AnTCODI AnTCRDI AnTCUQ AnTCAIS AnTCLM AnTCLL AnTCTM AnTCODI AnTCRDI An TC BIP-2 Error Counter An TC REI Counter An TC OEI Counter An Receive V4 Byte 0 0
* R=Read Only; R(L)=Read Only (Latched); R/W=Read/Write; W=Write Only.
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DATA SHEET
STATUS REGISTERS - PORT n (B SIDE) Address Port 1, 2, 3, 4
03A 06A 09A 0CA 03B 06B 09B 0CB 03C 06C 09C 0CC 03D 06D 09D 0CD 03E 06E 09E 0CE 03F 06F 09F 0CF 05E 08E 0BE 0EE 05F 08F 0BF 0EF 040 070 0A0 0D0 041 071 0A1 0D1 042 072 0A2 0D2 043 073 0A3 0D3 05C 08C 0BC 0EC 05D 08D 0BD 0ED 180 280 380 480 181 281 381 481 182 282 382 482 196 296 396 496
QE1M TXC-04252
Status* R(L) R R R R R R(L) R R R R R R(L) R R R R R
Bit 7 BnAIS BnAIS
Bit 6 BnLOP BnLOP
Bit 5 BnSIZE BnSIZE
Bit 4 BnNDF BnNDF
Bit 3 BnRDIS BnRDIS
Bit 2 BnRFI BnRFI
Bit 1
Bit 0
BnUNEQ BnSLER BnUNEQ BnSLER
BnPJ Counter BnBIP2 Error Counter BnFEBE Counter Unused BnRDIP BnRDIP BnRDIC BnRDIC Unused (00) Unused (00)
BnNJ Counter
Bn Rx Label BnJ2LOL BnJ2TIM BnJ2LOL BnJ2TIM Unused Unused Unused (00) Unused (00)
Bn Receive K4 (Z7) Byte Bn Receive O-Bits BnTCUQ BnTCAIS BnTCLM BnTCLL BnTCTM BnTCODI BnTCRDI BnTCUQ BnTCAIS BnTCLM BnTCLL BnTCTM BnTCODI BnTCRDI Bn TC BIP-2 Error Counter Bn TC REI Counter Bn TC OEI Counter Bn Receive V4 Byte 0 0
STATUS REGISTERS - PORT n (A AND B SIDES) Address Port 1, 2, 3, 4
044 074 0A4 0D4 045 075 0A5 0D5 046 076 0A6 0D6 047 077 0A7 0D7
Status* R(L) R R R
Bit 7 RnFFE RnFFE
Bit 6 0 0
Bit 5 ANAnOOL ANAnOOL
Bit 4 TAnFE TAnFE
Bit 3 TBnFE TBnFE
Bit 2 TnLOS TnLOS
Bit 1 TnLOC TnLOC
Bit 0 TnDAIS TnDAIS
Port n HDB3 Coding Errors (Low Byte) Port n HDB3 Coding Errors (High Byte)
* R=Read Only; R(L)=Read Only (Latched); R/W=Read/Write; W=Write Only.
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QE1M TXC-04252
DATA SHEET
OPERATIONS (CONTROL) REGISTERS - PORT n Address Port 1, 2, 3, 4
048 078 0A8 0D8 050 080 0B0 0E0 051 081 0B1 0E1 052 082 0B2 0E2 053 083 0B3 0E3 054 084 0B4 0E4 055 085 0B5 0E5 056 086 0B6 0E6 057 087 0B7 0E7 058 088 0B8 0E8 059 089 0B9 0E9 511 591 611 691
Status* R/W R/W R/W W R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7
Bit 6
Bit 5
Bit 4 1BnRDI TnAIS TCnEN
Bit 3
Bit 2
Bit 1
Bit 0
Unused (set to 000) FnLBK TCnRDI LnLBK RnAIS TCnODI TCnAIS
J2nTEN J2nSIZE J2nCOM J2nAISE TnVTAIS TCnRE TnRFI TCnOE TnRDIS TCnAEN TnFB2 TnRDIP TnRDIC TnFFB
RnSETS RnSETC
Unused (set to 0000)
Unused (set to 00000) Unused (set to 00000) Unused (set to 00000) Unused Unused Transmit K4 (Z7) Byte Value (4-7)
An P Mismatch Label Bn P Mismatch Label Tn TX Label
Unused (set to 000)
TZ7BV(0)
Transmit O-Bits - Port n Transmit V4 Bytes - Port n
J2 AND N2 (Z6) MESSAGE SEGMENTS - PORT n Address Port 1, 2, 3, 4 140 240 340 440 to 17F 27F 37F 47F Status* R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Port n A side J2 64-byte trace message received (X40 - X7F) or A side J2 16-byte trace message received (X40 - X4F) A side J2 16-byte microprocessor-written trace message (X50 - X5F) A side TC (N2 (Z6)) 16-byte trace message received (X60 - X6F) A side TC (N2 (Z6)) 16-byte microprocessor-written trace message (X70 - X7F) Port n B side J2 64-byte trace message received (XC0 - XFF) or B side J2 16-byte trace message received (XC0 - XCF) B side J2 16-byte microprocessor-written trace message (XD0 - XDF) B side TC (N2 (Z6)) 16-byte trace message received (XE0 - XEF) B side TC (N2 (Z6)) 16-byte microprocessor-written trace message (XF0 - XFF) Port n J2 64-byte trace message transmitted (540 - 57F Port 1, 5C0 - 5FF Port 2, 640 - 67F Port 3, 6C0 - 6FF Port 4) or J2 16-byte trace message transmitted (540-54F Port 1, 5C0-5CF Port 2, 640-64F Port 3, 6C0-6CF Port 4) TC (N2 (Z6)) 16-byte trace message transmitted (560-56F Port 1, 5E0-5EF Port 2, 660-66F Port 3, 6E0-6EF Port 4)
1C0 2C0 3C0 4C0 to 1FF 2FF 3FF 4FF
R/W
540 5C0 640 6C0 to 57F 5FF 67F 6FF
R/W
Where X = 1 for Port 1, 2 for Port 2, 3 for Port 3, 4 for Port 4. * R=Read Only; R(L)=Read Only (Latched); R/W=Read/Write; W=Write Only.
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DATA SHEET MEMORY MAP DESCRIPTIONS
COMMON REGISTERS - PROGRAM ID Address 6BD Bit 7-0 Symbol PID-CHK Description
QE1M TXC-04252
This value (register 6BEH + register 6BFH + 0x55) is written by SPOT during initialization, and at the start of each maintenance cycle (2 kHz rate). The external microprocessor can read this checksum to validate the revision numbers in registers 6BEH and 6BFH. By writing this location with a different value, waiting at least 1 ms, and then reading this location, the external microprocessor can determine whether the SPOT program is running. Part 1 of two-part program release number. Part 2 of two-part program release number.
6BE 6BF
*
7-0 7-0
PGMRV1* PGMRV2*
Registers 6BEH and 6BFH contain the two-part SPOT program release number. In documentation, this number is written as "PGMRV1, PGMRV2".
COMMON REGISTERS - INTERNAL PROCESSOR (SPOT) Address 005 006 Bit 7-0 7-0 Symbol Description TranSwitch Test Register: These bits must be written to 0.
SPOTPCLD Internal SPOT Processor Load Register: These bits are the lower 8
bits of the 11-bit register which is used as the offset address access for the SPOT Instruction RAM. During normal operation these bits must be written to 0. 007 7 RPSPOT Reprogram Internal SPOT Processor Control Bit: This bit is written to 1 for accessing the SPOT Instruction RAM. During normal operation this bit must be written to 0. TranSwitch Test Bits: These bits must be written to 0. SPOT PC Load Internal SPOT Processor Load Register: These bits are the upper 3 bits of the 11-bit register which is used as the offset address access for the SPOT Instruction RAM. During normal operation these bits must be written to 0. TranSwitch Test Register: These bits must be written to 0.
6-3 2-0
008
7-0
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QE1M TXC-04252
DATA SHEET
COMMON REGISTERS - CONTROL DESCRIPTIONS Address 010 Bit 7 6 Symbol MOD1 MOD0 Description Format Selection: The format selection is made according to the table given below. MOD1 0 0 1 1 5 AAHZE MOD0 0 1 0 1 Format Selected STS-1 Format STS-3 Format STM-1/AU-3 Format STM-1/TUG-3/VC-4 Format
A Add Bus High Impedance Enable: A 1 forces the A-side add bus data output to a high impedance state. Upon power-up, or on a hardware or software reset, this bit is set to a 1. Note: For normal bus operation this bit position must be written with a 0. See Note 1. B Add Bus High Impedance Enable: A 1 forces the B-side add bus data output to a high impedance state. Upon power-up, or on a hardware or software reset, this bit is set to a 1. Note: For normal bus operation this bit position must be written with a 0. See Note 1 Block Count: A 1 enables two BIP-2 errors to be counted as a single error (block) for the BIP-2 performance counters (V5 and K4 (Z7) bytes). A 0 enables two BIP-2 errors to be counted as two errors. Null Pointer Indicator Selection: A 1 enables a null pointer indicator to be generated for the corresponding TUG-3 when control bits MOD1 and MOD0 are a 1 (STM-1/TUG-3/VC-4 format). A null pointer indicator is carried in the first three bytes of column 1 in a TUG-3. The null pointer indicator byte values are 93H, E0H and 00H. A 0 forces the NPI byte position to a high impedance state on the A/B buses.
4
BAHZE
3
BLOCK
2 1 0
NPIA NPIB NPIC
Note 1: The add bus will be forced to a high impedance state automatically when loss of clock is detected on the transmit clock signal selected by control bit DBPBT.
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DATA SHEET
QE1M TXC-04252
Address 011
Bit 7
Symbol SBTEN
Description Software Bus Timing Enable: This bit works in conjunction with control bit DRPBT in bit 6 and the ABUST lead according to the following table (where X = Don't Care): SBTEN 0 DRPBT X ABUST Low Action Add bus timing selected. Add bus data derived from add bus timing signals. Software control of bus timing disabled. Drop bus timing selected. Add bus data derived from like-named drop bus. Software control of bus timing disabled. Add bus timing selected. Add bus data derived from add bus timing signals. Hardware control of bus timing disabled. Drop bus timing selected. Add bus data derived from like-named drop bus. Hardware control of bus timing disabled.
0
X
High
1
0
X
1
1
X
This SBTEN bit is reset to 0 upon power-up and by a device reset. 6 DRPBT Drop Bus Timing: Enabled when a 1 is written to control bit SBTEN. A 1 selects the drop bus timing mode, while a 0 selects the add bus timing mode. See table above. Add Bus Delay: A 0 delays the add bus data with respect to the drop bus by one clock cycle, when the drop bus or add bus timing modes are selected. A 1 delays the add bus data with respect to the drop bus or add bus by one additional clock cycle, for a total of two clock cycles. Latch On Transitions Enable Bit: A 0 disables the states of the IPOS and INEG control bits, and causes the event alarm bits (latched alarm bits in the registers) to latch on the positive (1) level of an alarm. A 1 enables the states of the IPOS and INEG control bits in register 012H. Transmit E1 Line AIS Enable: A common control for all four ports. A 1 enables an E1 AIS (unframed all ones) to be generated and sent from port n to the SDH/SONET side when an E1 line input loss of signal, or loss of clock, occurs for port n. Transmit E1 Line Clock Inversion: A common control for the four ports. A 0 enables transmit data to be clocked in on the negative (falling) clock edges. A 1 enables transmit data to be clocked in on the positive (rising) clock edges.
5
ABD
4
LATEN
3
TAISE
2
TCLKI
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QE1M TXC-04252
DATA SHEET
Address 011 (cont.)
Bit 1
Symbol RAISE
Description Receive E1 Line AIS Enable: A common control for the four ports. A 1 enables a receive E1 AIS to be sent from port n when internal defined alarms occur for a port n. An E1 AIS is an unframed all ones signal. For example, receive AIS for port 1 will be generated:
- When R1SEL is 0 and any of: - Loss of pointer detected (A1LOP) - VT AIS detected (A1AIS) - A Drop Bus Loss Of Clock (ADLOC) - A Drop Bus Upstream AIS detected (AsUAISI) when HEAISE is 1. - or when R1SEL is 0 and RAISE is 1 (drop VT from A side) and any of: - A Drop H4 Error (AsDH4E) when DV1SEL is 0 - Unequipped signal label (A1UNEQ) and UQAE is 1 - Mismatch signal label (A1SLER) - J2 Loss Of Lock Alarm (A1J2LOL) when J21COM and J21AISE are 1, and J21SIZE=0 - J2 Mismatch Alarm (A1J2TIM) when J21COM and J21AISE are 1, and J21SIZE=0 - TC Unequipped Alarm (A1TCUQ) when TC1EN and TC1AEN are 1 - TC Loss Of Lock Alarm (A1TCLL) when TC1EN and TC1AEN are 1 - TC Mismatch Alarm (A1TCTM) when TC1EN and TC1AEN are 1 - TC Loss Of Multiframe Alarm (A1TCLM) when TC1EN and TC1AEN are 1 - TC AIS Detected (A1TCAIS) when TC1EN and TC1AEN are 1. - or when R1SEL is a 1 and any of: - Loss of pointer detected (B1LOP) - VT AIS detected (B1AIS) - B Drop Bus Loss Of Clock (BDLOC) - B Drop Bus Upstream AIS detected (BsUAISI) and HEAISE is 1. - or when R1SEL is 1 and RAISE is 1 (drop VT from B side) and any of: - B Drop H4 Error (BsDH4E) when DV1SEL is 0 - Unequipped signal label (B1UNEQ) and UQAE is 1 - Mismatch signal label (B1SLER) - J2 Loss Of Lock Alarm (B1J2LOL) when J21COM and J21AISE are 1, and J21SIZE=0. - J2 Mismatch Alarm (B1J2TIM) when J21COM and J21AISE are 1, and J21SIZE=0 - TC Unequipped Alarm (B1TCUQ) when TC1EN and TC1AEN are 1 - TC Loss Of Lock Alarm (B1TCLL) when TC1EN and TC1AEN are 1 - TC Mismatch Alarm (B1TCTM) when TC1EN and TC1AEN are 1 - TC Loss Of Multiframe Alarm (B1TCLM) when TC1EN and TC1AEN are 1 - TC AIS Detected (B1TCAIS) when TC1EN and TC1AEN are 1. - or when Receive FIFO Error (R1FFE) and RAISE are 1. - or when a 1 is written to send receive AIS (R1AIS). - or when RTUN1 is invalid.
The AIS will be sent for one multiframe when a receive FIFO error occurs. The s in AsUAISI, BsUAISI, AsDH4E and BsDH4E represents the STS-1 or TUG in which the TU/VT has been selected, where s = 1-3. 0 RCLKI Receive E1 Line Clock Inversion: A common control for the four ports. A 0 enables the E1 receive data signal to be clocked out on positive (rising) RCOn clock edges. A 1 causes E1 data to be clocked out on negative (falling) RCOn clock edges.
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DATA SHEET
QE1M TXC-04252
Address 012
Bit 7
Symbol ADDI
Description Add Indicator Inversion: A 1 causes the A and B Add bus output indicator signals (AADD and BADD) to be active high instead of active low when a time slot is added to the bus. A/B Add Bus Even Parity Generated: A 1 enables even parity to be generated, while a 0 enables odd parity to be generated. Parity is calculated over the data byte only. Interrupt/Event Positive/Negative Alarm Transition Selection: An event register bit will latch, and a software interrupt indication will occur, according to the transitions given in the table below. The appropriate interrupt mask bit(s) must be set if an interrupt is required. A hardware interrupt occurs when the hardware interrupt bit is also enabled (control bit HDWIE is 1). These bits are disabled when a 0 is written to control bit LATEN. IPOS 0 1 0 1 INEG 0 0 1 1 Action No event or interrupt indication Event and interrupt on positive alarm transition Event and interrupt on negative alarm transition Event and interrupt on both positive and negative alarm transitions
6
APE
5 4
IPOS INEG
3
RFIE
RFI Enable: A common control bit for all four ports. A 1 enables an RFI indication to cause an interrupt. A 0 disables an RFI indication (bit 4 in V5 of the TU/VT) from causing an interrupt. Threshold Modulation Disabled: A 1 disables the threshold modulation capability in each of the four modulation circuits. A 0 enables threshold modulation capability in each of the four modulation circuits. A/B Drop Bus Even Parity Detected: This bit works in conjunction with the PDDO control bit to determine the parity calculation in the drop direction. DPE 0 0 1 1 PDDO 0 1 0 1 Action (for both A and B buses) Odd parity check over drop data, SPE, and C1J1V1. Odd parity check over drop data only. Even parity check over drop data, SPE, and C1J1V1. Even parity check over drop data only.
2
THRSBY
1
DPE
Other than reporting the event, no action is taken upon parity error indication. 0 PDDO A/B Drop Bus Parity Detected on Data Only: Common control bit for both buses. A 1 causes parity to be calculated over the data byte only. A 0 causes parity to be calculated over the data byte, SPE and C1J1V1 signals. Please refer to the table provided for DPE.
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QE1M TXC-04252
DATA SHEET
Address 013
Bit 7
Symbol HEAISE
Description A/B H1/H2 or E1 Byte AIS Enable: Common control for both the A and B Drop buses. A 1 enables an AIS detected in either the SDH/SONET H1/H2 bytes, or in the E1 bytes, to generate a receive E1 line AIS and transmit an RDI (when enabled). Drop Bus V1 Reference Enable: Common control bit for both buses. In the Drop Bus Timing Mode this bit must be set to zero. In the Add Bus Timing Mode this control bit works in conjunction with the DV1REF control bit according to the following table. Drop Bus V1 Reference Enable: Common control bit for both buses. Enabled when add bus timing is selected. This control bit works in conjunction with the DV1SEL control bit according to the following table: DV1SEL 0 DV1REF 0 Action Drop side uses H4 multiframe detector to determine V1 pulse Add side uses V1 pulse from add bus C1J1V1 signal Drop side uses H4 multiframe detector to determine V1 pulse Add side uses V1 pulse from drop side H4 multiframe detector Drop side uses V1 pulse from drop bus C1J1V1 signal Add side uses V1 pulse from add side C1J1V1 signal Drop side uses V1 pulse from drop side C1J1V1 signal Add side uses V1 pulse from drop side C1J1V1 signal
6
DV1SEL
5
DV1REF
0
1
1
0
1
1
4
RDIEN
Transmit Remote Defect Indication Enable: Common control for both buses. This control bit enables incoming receive side (Drop) alarms to generate a Remote Defect Indication in the transmit (Add) direction. This bit also works in conjunction with the control bit 1BnRDI found in the Operations (Control) Registers (048H, 078H, 0A8H, 0D8H). More details of how these control bits function can be found in the Operation Section on Remote Defect Indications. Force the NPI Column Unused Bytes to Zero: A 1 forces to 00H the unused bytes in the column following the NPI bytes when the NPI feature is enabled for the same TUG-3 (NPIA, NPIB or NPIC is a 1). A 0 forces the unused bytes following the NPI to a high impedance state on the A/B buses. Delay Drop Bus Indication Signal: A 1 increases the delay of the drop bus indication signals (ADIND and BDIND) by one clock cycle. Unequipped Alarm AIS/RDI/TC Alarm Enable: A common control for both the A and B Drop buses. A 1 enables a receive E1 line AIS, an RDI and both of the TC alarms (TCnODI, TCnRDI) to be transmitted when an unequipped alarm is detected in either the A or B Drop bus signals. Transmit O-Bit Channel With Zeros: A common control for all four ports. A 0 enables the microprocessor-written values for the O-bit channel and the unused bits in the K4 (Z7) byte to be transmitted. A 1 forces the O-bit channel and the unused bits in the K4 (Z7) byte to be transmitted as zero for all four ports.
3
NULLZ
2 1
DDIND UQAE
0
TOBWZ
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DATA SHEET
COMMON REGISTERS - PROVISIONING DESCRIPTIONS Address 014 Bit 7-5 4 Symbol Unused UEAME Description Unused: These bits must be written to 0.
QE1M TXC-04252
Unequipped All Modes Enable: A 0 enables an unequipped channel or an unequipped supervisory channel to be generated in the Multiplexer Mode only, according to the table given below: Drop Add Action A B Unequipped or unequipped supervisory channel can be transmitted for the TU/VT selected on the A Bus. B A Unequipped or unequipped supervisory channel can be transmitted for the TU/VT selected on the B Bus. A 1 enables an unequipped channel or unequipped supervisory channel to be transmitted only on the active bus for the TU/VT selected. See control bits UCHnE and USCHnE below (Addresses 04A, 07A, 0AA, 0DA) for associated control functions. Select E1AIS: A 1 disables the TOH H1/H2n AIS detection circuit and enables the AIS detection circuit for the TOH E1n bytes. A 0 enables the AIS detection circuit for the H1/H2n bytes. Here the value of n is 1 for an STM-1 format and 1, 2 or 3 for an AU-3/STS-1 signal. V5 Alarm Detection Select 10: A 1 selects 10 consecutive RDI assertions for detection and recovery. A 0 selects 5 consecutive RDI assertions for detection and recovery. Pointer Tracking AIS to LOP Transition Enabled: A 1 enables the AIS to LOP transition in the pointer tracking state machine, as required by ETSI standards. A 0 will disable the transition, as required by Bellcore and ANSI standards. Hardware Interrupt Enable: A 1 enables the interrupt lead to be activated when an interrupt occurs. Reset: A 1 clears to zero all controls, alarms, internal counters and performance counters, sets control bits AAHZE and BAHZE to 1, and re-initializes the receive and transmit FIFOs. This bit is self-clearing, and will reset to 0 after the reset cycle is completed. See Note 1. Reset A Side Bus Alarms: A 1 clears the alarms associated with the A side bus and the LEXTC alarm. This bit is self-clearing, and will reset to 0 after the reset cycle is completed. See Note 2. Reset B Side Bus Alarms: A 1 clears the alarms associated with the B side bus and SPOT alarms. This bit is self-clearing, and will reset to 0 after the reset cycle is completed. See Note 2. Reset Internal Processor (SPOT): A 1 resets the SPOT processor, without affecting its RAM. This bit will reset itself to 0 after the reset cycle is completed. See Note 1. Unused: These bits must be written to 0. Initialize Internal Processor (SPOT) Data RAM: A 1 initializes the Data RAM associated with the SPOT processor and resets the general purpose registers of this processor. This bit should only be set to 1 after a hardware reset (lead 155 or C5) or a software reset (control bit RESET above) has been activated. This bit is self-clearing and will reset to 0 after the Data RAM initialization is complete. See Note 1.
3
SE1AIS
2
V5AL10
1
PTALTE
0 015 7
HDWIE RESET
6
RESTAB
5
RESTBB
4
RESTSP
3-1 0
Unused INITSP
Note 1: The control bits RESET, RESTSP and INITSP in address 015H should not be applied simultaneously, but only serially (e.g., 80H followed by 01H, rather than 81H). Note 2: Control bits RESTAB and RESTBB may be applied at the same time (60H).
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QE1M TXC-04252
DATA SHEET
COMMON REGISTERS - INTERRUPT INDICATION REGISTER DESCRIPTIONS Address 020 Bit 7 6 Symbol INT EXTCK Description Software Interrupt Indication: A 1 indicates that a latched alarm has occurred for which the corresponding interrupt mask bit(s) is/are set to 1. External Clock Interrupt Indication: Enabled when a 1 is written into the ECKMSK bit. A 1 indicates that the external clock at input lead EXTCK has failed (i.e., LEXTC=1). A Side Interrupt Indication: Enabled when a 1 is written into the ASMSK bit. A 1 indicates that an alarm has occurred in one of the A-side alarm registers (i.e., 022H and 024H, bits 2, 1 and 0). B Side Interrupt Indication: Enabled when a 1 is written into the BSMSK bit. A 1 indicates that an alarm has occurred in one of the B-side alarm registers (i.e., 026H and 028H, bits 2, 1 and 0). Port 4 Interrupt Indication: Enabled when a 1 is written into the P4MSK bit. A 1 indicates that an alarm has occurred in one of the port 4 alarm registers for which the corresponding additional interrupt mask bit is also set to 1 (addresses 017H, 018H and 019H). Port 3 Interrupt Indication: Enabled when a 1 is written into the P3MSK bit. A 1 indicates that an alarm has occurred in one of the port 3 alarm registers for which the corresponding additional interrupt mask bit is also set to 1 (addresses 017H, 018H and 019H). Port 2 Interrupt Indication: Enabled when a 1 is written into the P2MSK bit. A 1 indicates that an alarm has occurred in one of the port 2 alarm registers for which the corresponding additional interrupt mask bit is also set to 1 (addresses 017H, 018H and 019H). Port 1 Interrupt Indication: Enabled when a 1 is written into the P1MSK bit. A 1 indicates that an alarm has occurred in one of the port 1 alarm registers for which the corresponding additional interrupt mask bit is also set to 1 (addresses 017H, 018H and 019H).
5
ASIDE
4
BSIDE
3
PORT4
2
PORT3
1
PORT2
0
PORT1
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COMMON REGISTERS - INTERRUPT MASK DESCRIPTIONS Address 016 Bit 7-1 0 Symbol Unused SPTMSK Description Unused: These bits must be written to 0.
QE1M TXC-04252
SPOT Status Interrupt Mask: A 1 enables a hardware interrupt (lead INT/IRQ) and a software interrupt indication (INT) when a SPOT alarm has occurred in any of the SPOT alarm register bits (address 028H, bits 7, 6 and 4). A 0 disables the SPOT alarms from causing an interrupt. See Note 1. Receive A Side Status Interrupt Mask Bit: A 1 enables a hardware interrupt and software interrupt indication (INT) when an alarm has occurred in an A-side port n alarm register while PnMSK is set for port n. A 0 disables the A side receive alarms for port n from causing an interrupt. See Note 1. Receive B Side Status Interrupt Mask Bit: A 1 enables a hardware interrupt and software interrupt indication (INT) when an alarm has occurred in a B-side port n alarm register while PnMSK is set for port n. A 0 disables the B side receive alarms for port n from causing an interrupt. See Note 1. Transmit FIFO Error A Side Status Interrupt Mask Bit: A 1 enables a hardware interrupt and software interrupt indication (INT) when an alarm has occurred for an A-side port n transmit FIFO while PnMSK is set for port n. A 0 disables a transmit FIFO error A side alarm for port n from causing an interrupt. See Note 1. Transmit FIFO Error B Side Status Interrupt Mask Bit: A 1 enables a hardware interrupt and software interrupt indication (INT) when an alarm has occurred for a B-side port n transmit FIFO while PnMSK is set for port n. A 0 disables a transmit FIFO error B side alarm for port n from causing an interrupt. See Note 1. Transmit Status Interrupt Mask Bit: A 1 enables a hardware interrupt and software interrupt indication (INT) when an alarm has occurred for one of the port n transmit alarms while PnMSK is set for port n. A 0 disables a transmit alarm from causing an interrupt. See Note 1. Receive FIFO Error Status Interrupt Mask Bit: A 1 enables a hardware interrupt and software interrupt indication (INT) when an alarm has occurred for a port n receive FIFO while PnMSK is set for port n. A 0 disables a receive FIFO error alarm for port n from causing an interrupt. See Note 1.
017
7, 5, 3, 1
RPTnA (n=4-1)
6, 4, 2, 0
RPTnB (n=4-1)
018
7, 5, 3, 1
TFIFOnA (n=4-1)
6, 4, 2, 0
TFIFOnB (n=4-1)
019
7, 6, 5, 4
TPORTn (n=4-1)
3, 2, 1, 0
RFIFOn (n=4-1)
Note 1: Please refer to the tables in the Operation - Interrupt Structure section for the specific alarms and register locations to which these interrupt masks apply. RPTnA or RPTnB is not required to be set to 1 to enable an interrupt for AnRFI or BnRFI alarms. Control bit HDWIE must be set to 1 if a hardware interrupt is required.
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QE1M TXC-04252
DATA SHEET
Address 021
Bit 7 6
Symbol Unused ECKMSK
Description Unused: This bit must be written to 0. External Clock Interrupt Mask Bit: A 1 enables a hardware interrupt and software interrupt indications (INT and ETXCK) when an external clock failure alarm has occurred. See Note 1. A Side Interrupt Mask Bit: A 1 enables the A Side Interrupt Indication (ASIDE). See Note 1. B Side Interrupt Mask Bit: A 1 enables the B Side Interrupt Indication (BSIDE). See Note 1. Port 4 Interrupt Mask Bit: A 1 enables the Port 4 Interrupt Indication (PORT4). It permits a hardware interrupt and a software interrupt indication (INT) when an alarm has occurred in one of the alarm registers for port 4, when the corresponding RPT4A, RPT4B, TFIFO4A, TFIFO4B, RFIFO4 or TPORT4 mask bit is set to 1. See Note 1. Port 3 Interrupt Mask Bit: A 1 enables the Port 3 Interrupt Indication (PORT3). It permits a hardware interrupt and a software interrupt indication (INT) when an alarm has occurred in one of the alarm registers for port 3, when the corresponding RPT3A, RPT3B, TFIFO3A, TFIFO3B, RFIFO3 or TPORT3 mask bit is set to 1. See Note 1. Port 2 Interrupt Mask Bit: A 1 enables the Port 2 Interrupt Indication (PORT2). It permits a hardware interrupt and a software interrupt indication (INT) when an alarm has occurred in one of the alarm registers for port 2, when the corresponding RPT2A, RPT2B, TFIFO2A, TFIFO2B, RFIFO2 or TPORT2 mask bit is set to 1. See Note 1. Port 1 Interrupt Mask Bit: A 1 enables the Port 1 Interrupt Indication (PORT1). It permits a hardware interrupt and a software interrupt indication (INT) when an alarm has occurred in one of the alarm registers for port 1, when the corresponding RPT1A, RPT1B, TFIFO1A, TFIFO1B, RFIFO1 or TPORT1 mask bit is set to 1. See Note 1.
5 4 3
ASMSK BSMSK P4MSK
2
P3MSK
1
P2MSK
0
P1MSK
Note 1: Please refer to the tables in the Operation - Interrupt Structure section for the specific alarms and register locations to which these interrupt masks apply. RPTnA or RPTnB is not required to be set to 1 to enable an interrupt for AnRFI or BnRFI alarms. Control bit HDWIE must be set to 1 if a hardware interrupt is required.
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A/B DROP AND ADD BUS - STATUS REGISTER DESCRIPTIONS Address 022 023 Bit 7-0 7 ADLOC Symbol Description
QE1M TXC-04252
Same bit definitions as in register 023 hex, except the bits are latched. A Drop Bus Loss Of Clock: A 1 indicates that the A Drop bus has detected a loss of clock. An alarm occurs when the input drop clock is stuck high or low for 1000 ns +/- 500 ns. Recovery to 0 occurs on the first clock transition. Please note that an alarm will force the add bus data and parity bits to a high impedance state, and will set the add indicator off for the duration of the alarm, when the drop bus timing mode is selected. A Add Bus Loss Of Clock: A 1 indicates that the A Add bus has detected a loss of clock, when add bus timing is selected. A loss of clock alarm forces the add bus data and parity bit to a high impedance state, and sets the add indicator off for the duration of the alarm. An alarm occurs when the input add clock is stuck high or low for 1000 ns +/- 500 ns. Recovery to 0 occurs on the first clock transition. A Drop Bus Parity Error Detected: A 1 indicates that an even or odd parity error has been detected in the A Drop bus signals. Other than an alarm indication, no action is taken. Parity is monitored for each drop bus clock cycle. Unused: These bits read out as 0. A Side Received Upstream AIS Indication - AU-3 C/STS-1 No. 3: When control bit SE1AIS is 0, a 1 indicates that AIS has been detected in the H1/H2 bytes for AU-3 C/STS-1 No. 3. When control bit SE1AIS is 1, a 1 indicates that AIS has been detected in the E13 byte for AU-3 C/STS-1 No. 3. Disabled when the format is an AU-4 VC-4, or STS-1. A Side Received Upstream AIS Indication - AU-3 B/STS-1 No. 2: When control bit SE1AIS is 0, a 1 indicates that AIS has been detected in the H1/H2 bytes for AU-3 B/STS-1 No. 2. When control bit SE1AIS is 1, a 1 indicates that AIS has been detected in the E12 byte for AU-3 B/STS-1 No. 2. Disabled when the format is an AU-4 VC-4, or STS-1. A Side Received Upstream AIS Indication - AU-3 A/STS-1 No. 1, AU-4 VC-4, or STS-1: When control bit SE1AIS is 0, a 1 indicates that AIS has been detected in the H1/H2 bytes for AU-3 A/STS-1 No. 1, or in the AU-4 VC-4 signal. When control bit SE1AIS is 1, a 1 indicates that AIS has been detected in the E11 byte for AU-3 A/STS-1 No. 1, AU-4 VC-4, or the STS-1 signal. Same bit definitions as in register 025 hex, except the bits are latched.
6
AALOC
5
ADPAR
4-3 2
Unused A3UAISI
1
A2UAISI
0
A1UAISI
024
7-0
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QE1M TXC-04252
DATA SHEET
Address 025
Bit 7
Symbol LEXTC
Description Loss Of External Clock: A 1 indicates an external loss of clock alarm when the external clock (present on lead 138) is stuck high or low for 1000 ns +/- 500 ns. Recovery to 0 occurs on the first clock transition. Unused: These bits read out as 0. A Drop Bus Loss of H4 Indication - AU-3 C/STS-1 No. 3: Loss of multiframe for AU-3 C/STS-1 No. 3 is declared if one or more H4 values differ from those of a two-bit counter once per multiframe for two consecutive multiframes, when control bit DV1SEL is 0. The received H4 multiframe sequence is 00, 01, 10, and 11. The multiframe detector will continue to operate in a free running mode, but will lock to a new H4 sequence after one multiframe sequence has been received correctly. This H4 detector is disabled when the format is an AU-4 VC-4, or STS-1. This bit is forced to 1 at power-up. A Drop Bus Loss of H4 Indication - AU-3 B/STS-1 No. 2: Loss of multiframe for AU-3 B/STS-1 No. 2 is declared if one or more H4 values differ from those of a two-bit counter once per multiframe for two consecutive multiframes, when control bit DV1SEL is 0. The received H4 multiframe sequence is 00, 01, 10, and 11. The multiframe detector will continue to operate in a free running mode, but will lock to a new H4 sequence after one multiframe sequence has been received correctly. This H4 detector is disabled when the format is an AU-4 VC-4, or STS-1. This bit is forced to 1 at power-up. A Drop Bus Loss of H4 Indication - AU-3 A/STS-1 No. 1, AU-4 VC-4, or STS-1: Loss of multiframe for AU-3 A/STS-1 No. 1, AU-4 VC-4 or STS-1 is declared if one or more H4 values differ from those of a two-bit counter once per multiframe for two consecutive multiframes, when control bit DV1SEL is 0. The received H4 multiframe sequence is 00, 01, 10, and 11. The multiframe detector will continue to operate in a free running mode, but will lock to a new H4 sequence after one multiframe sequence has been received correctly. This bit is forced to 1 at power-up. Same bit definitions as in register 027 hex, except the bits are latched.
6-3 2
Unused A3DH4E
1
A2DH4E
0
A1DH4E
026
7-0
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QE1M TXC-04252
Address 027
Bit 7
Symbol BDLOC
Description B Drop Bus Loss Of Clock: A 1 indicates that the B Drop bus has detected a loss of clock. An alarm occurs when the input drop clock is stuck high or low for 1000 ns +/- 500 ns. Recovery to 0 occurs on the first clock transition. Please note that an alarm will force the add bus data and parity bits to a high impedance state, and will set the add indicator off for the duration of the alarm, when the drop bus timing mode is selected. B Add Bus Loss Of Clock: A 1 indicates that the B Add bus has detected a loss of clock, when add bus timing is selected. A loss of clock alarm forces the add bus data and parity bit to a high impedance state, and sets the add indicator off for the duration of the alarm. An alarm occurs when the input drop clock is stuck high or low for 1000 ns +/- 500 ns. Recovery to 0 occurs on the first clock transition. B Drop Bus Parity Error Detected: A 1 indicates that an even or odd parity error has been detected in the B Drop bus signals. Other than an alarm indication, no action is taken. Parity is monitored for each drop bus clock cycle. Unused: These bits read out as 0. B Side Received Upstream AIS Indication - AU-3 C/STS-1 No. 3: When control bit SE1AIS is 0, a 1 indicates that AIS has been detected in the H1/H2 bytes for AU-3 C/STS-1 No. 3. When control bit SE1AIS is 1, a 1 indicates that AIS has been detected in the E13 byte for AU-3 C/STS-1 No. 3. Disabled when the format is a AU-4 VC-4, or STS-1. B Side Received Upstream AIS Indication - AU-3 B/STS-1 No. 2: When control bit SE1AIS is 0, a 1 indicates that AIS has been detected in the H1/H2 bytes for AU-3 B/STS-1 No. 2. When control bit SE1AIS is 1, a 1 indicates that AIS has been detected in the E12 byte for AU-3 B/STS-1 No. 2. Disabled when the format is a AU-4 VC-4, or STS-1 B Side Received Upstream AIS Indication - AU-3 A/STS-1 No. 1, AU-4 VC-4, or STS-1: When control bit SE1AIS is 0, a 1 indicates that AIS has been detected in the H1/H2 bytes for AU-3 A/STS-1 No. 1, or in the AU-4 VC-4 signal. When control bit SE1AIS is 1, a 1 indicates that AIS has been detected in the E11 byte for AU-3 A/STS-1 No. 1, AU-4 VC-4, or the STS-1 signal. Same bit definitions as in register 029 hex, except the bits are latched.
6
BALOC
5
BDPAR
4-3 2
Unused B3UAISI
1
B2UAISI
0
B1UAISI
028
7-0
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QE1M TXC-04252
DATA SHEET
Address 029
Bit 7
Symbol SPTLOC
Description Internal Processor (SPOT) Loss of Clock: The 29.16 MHz clock internally derived from the 58.32 MHz desynchronizer clock input (EXTCK) is monitored for loss of clock. Loss of clock is declared if this clock is stuck high or low for 1000 +/- 500 ns. Recovery to 0 occurs on the first clock transition. Watch Dog Timer Expired: This bit is set to 1 when the SPOT is unable to service all requests in a timely manner. Unused: This bits reads out as 0. Parity Error: This bit is set to 1 when a parity error is detected while reading the Instruction RAM of the SPOT. Unused: This bits reads out as 0. B Drop Bus Loss of H4 Indication - AU-3 C/STS-1 No. 3: Loss of multiframe for AU-3 C/STS-1 No. 3 is declared if one or more H4 values differ from those of a two-bit counter once per multiframe for two consecutive multiframes, when control bit DV1SEL is 0. The received H4 multiframe sequence is 00, 01, 10, and 11. The multiframe detector will continue to operate in a free running mode, but will lock to a new H4 sequence after one multiframe sequence has been received correctly. This H4 detector is disabled when the format is an AU-4 VC-4, or STS-1. This bit is forced to 1 at power-up. B Drop Bus Loss of H4 Indication - AU-3 B/STS-1 No. 2: Loss of multiframe for AU-3 B/STS-1 No. 2 is declared if one or more H4 values differ from those of a two-bit counter once per multiframe for two consecutive multiframes, when control bit DV1SEL is 0. The received H4 multiframe sequence is 00, 01, 10, and 11. The multiframe detector will continue to operate in a free running mode, but will lock to a new H4 sequence after one multiframe sequence has been received correctly. This H4 detector is disabled when the format is an AU-4 VC-4, or STS-1. This bit is forced to 1 at power-up. B Drop Bus Loss of H4 Indication - AU-3 A/STS-1 No. 1, AU-4 VC-4, or STS-1: Loss of multiframe for AU-3 A/STS-1 No. 1, AU-4 VC-4 or STS-1 is declared if one or more H4 values differ from those of a two-bit counter once per multiframe for two consecutive multiframes, when control bit DV1SEL is 0. The received H4 multiframe sequence is 00, 01, 10, and 11. The multiframe detector will continue to operate in a free running mode, but will lock to a new H4 sequence after one multiframe sequence has been received correctly. This bit is forced to 1 at power-up.
6 5 4 3 2
WDTEXP Unused PERR Unused B3DH4E
1
B2DH4E
0
B1DH4E
PORT n - DESYNCHRONIZER CONTROL REGISTER DESCRIPTIONS Address 049 Port 1 079 Port 2 0A9 Port 3 0D9 Port 4 Bit 7-0 Symbol Pointer Leak Rate Value Description Desynchronizer Pointer Leak Rate Register - Port n: The count written into this location is used for the internal leak rate buffer, and represents the average leak rate. A count of one represents 8 frames, or 2 multiframes, in the rate of occurrence of pointer movements from the number of counts read from the positive and negative stuff counters.
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PORT n - PROVISIONING REGISTER DESCRIPTIONS Address 04A Port 1 07A Port 2 0AA Port 3 0DA Port 4 Bit 7 6 5 Symbol TnSEL1 TnSEL0 RnSEL Description
QE1M TXC-04252
Transmit Port n A/B Drop/Add Bus Selection: The table below lists the selection criteria for the eight available modes of operation of port n: 7 0 0 0 0 1 1 1 1 6 0 0 1 1 0 0 1 1 5 0 1 0 1 0 1 0 1 Operating Mode A Drop only (Drop) B Drop only (Drop) A Drop A Add (Single Unidirectional Ring) B Drop B Add (Single Unidirectional Ring) A Drop B Add (Multiplexer) B Drop A Add (Multiplexer) A Drop A and B Add (Dual Unidirectional Ring) B Drop B and A Add (Dual Unidirectional Ring)
4
UCHnE
Unequipped Channel for Port n Enabled: The UCHnE control bit works in conjunction with the USCHnE control bit (in bit position 3) according to the following table: UCHnE 0 1 USCHnE X 0 Action Normal Operation. Unequipped TU/VT generated. An unequipped TU/VT consists of a normal NDF, size bits equal to 10, a fixed pointer equal to 105, and all other bytes equal to 00H. Unequipped supervisory TU/VT generated. An unequipped supervisory TU/VT consists of a normal NDF, size bits equal to 10, a fixed pointer equal to 105, and a valid J2 byte. The V5 byte will consist of a valid BIP-2, with the signal label sent as zeros by setting control bit TnTx Label to 0. The N2 (Z6) byte can be sent as zero by setting TCnEN=0 and TxB2DIS=1. The K4 (Z7) byte, bits 1, 2, 3, 4 and 8 can be sent as zeros by setting control bit TOBWZ=1. The RDI bits, V5 bit 8 and K4 (Z7) bits 5, 6 and 7 can be disabled and sent as zeros by setting control bit RDIEN=0.
1
1
Note: X = don't care (0 or 1). 3 2 1 USCHnE BYPASn RnEN Unequipped Supervisory Channel for Port n Enabled: Works in conjunction with the UCHnE bit according to the table given above. Bypass Codec of Port n: A 1 disables the HDB3 Codec (coder and decoder) of port n for NRZ operation. A 0 enables the HDB3 Codec. Receive Port n Enable: A 1 enables the receive data (NRZ or rail) output and clock output for port n when lead QUIETn is low. A 0 forces the data and clock output leads to a high impedance state. The four bits power up as 0 and are reset to 0. A 1 must be written to these control bits to enable the port E1 outputs. Unused: This bit must be written to 0.
0
Unused
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QE1M TXC-04252
DATA SHEET
Address 04B Port 1 07B Port 2 0AB Port 3 0DB Port 4
Bit 7
Symbol ADnEN
Description A Side Drop Bus Port n TU/VT Selection Output Enable: A 1 enables the drop bus ADIND signal output. This signal will be active low for the time slots corresponding to the TU/VT selected for port n. B Side Drop Bus Port n TU/VT Selection Output Enable: A 1 enables the drop bus BDIND signal output. This signal will be active low for the time slots corresponding to the TU/VT selected for port n. A Side Add Bus Port n TU/VT Selection Output Enable: A 1 enables the add bus AAIND signal output. This signal will be active low for the time slots corresponding to the TU/VT selected for port n. B Side Add Bus Port n TU/VT Selection Output Enable: A 1 enables the add bus BAIND signal output. This signal will be active low for the time slots corresponding to the TU/VT selected for port n. PRBS Analyzer Sampling Tx E1 Signal: A 1 enables the internal PRBS analyzer to sample the Tx E1 signal to be sent to the synchronizer. A 0 enables the internal PRBS analyzer to sample the E1 signal to be sent to the Rx E1 ports. PRBS Analyzer Enable: A1 enables the internal 215-1 PRBS analyzer. A 0 disables the analyzer. PRBS Generator Enable: A 1 enables the internal 215-1 PRBS generator. A 0 disables the generator. FEBE and RDI Disabled For Port n: Enabled when the single unidirectional mode (control bits TnSEL1, TnSEL0 are equal to 01) is selected. A 1 disables receive side alarms or an out of range condition from generating an RDI. In addition, the REI (FEBE) value is transmitted as a zero. Unused: This bit must be written to 0. Receive TU/VT Selection for Port n: The seven-bit binary code written into this location selects the TU/VT that is to be dropped from the A and/or B-side drop bus. Control bits TSEL1, TSEL0 and RSEL determine the drop bus(es) that the data is dropped from. If no TU/VT is selected, the microprocessor should either write a 1 to control bit RnAIS, thereby forcing an E1 AIS, or should write a 0 to RnEN, which will tristate the port n data and clock output leads. Also, the FEBE and RDI values are transmitted as zero. Unused: This bit must be written to 0. Transmit TU/VT Selection for Port n: The seven-bit binary code written into this location selects the TU/VT that is to be added to the A and/or B-side add bus. Control bits TSEL1, TSEL0 and RSEL determine the add bus(es) that the data is added to. If no TU/VT is selected, the A or B add bus will tristate. Unused: These bits must be written to 0. V4EN: A 1 enables the V4 access function in both receive and transmit directions. Unused: These bits must be written to 0.
6
BDnEN
5
AAnEN
4
BAnEN
3
ANAnTx
2 1 0
ANAnEN PRBSnEN FRDISn
04C Port 1 07C Port 2 0AC Port 3 0DC Port 4
7 6-0
Unused RTUNn
04D Port 1 07D Port 2 0AD Port 3 0DD Port 4
7 6-0
Unused TTUNn
0F1
7-4 3 2-0
Unused V4EN Unused
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QE1M TXC-04252
Address 0F5
Bit 7
Symbol TxB2DIS
Description Transmit BIP-2 Disable (Test Bit): A 0 is used for normal operation and will allow the calculated N2 (Z6) BIP-2 and V5 BIP-2 values to be transmitted. A 1 will disable N2 (Z6) BIP-2 calculation as well as V5 BIP-2 calculation for all 4 ports and output zeros in its place. Unused: These bits must be written to 0.
6-0
Unused
PORT n - RECEIVE STATUS REGISTER AND COUNTER DESCRIPTIONS The following descriptions pertain to the status registers and counters assigned to Port n. The status registers provide two readable bit positions per alarm. One bit (in an odd-numbered address) indicates the detected alarm as unlatched. The second bit (in the preceding even-numbered address) provides the alarm status as an latched alarm indication. A latched bit position is set on positive, negative, or both positive and negative transitions of the alarm, or on a positive level of the alarm. A latched alarm is cleared on a microprocessor read cycle of its address. During a read cycle for a counter, internal logic holds any increment to the counter until the read cycle is complete, and then updates the counter afterwards. Address 030 Port 1 060 Port 2 090 Port 3 0C0 Port 4 031 Port 1 061 Port 2 091 Port 3 0C1 Port 4 Bit 7-0 Symbol Latched An Alarms AnAIS AnLOP Description Same alarms as the unlatched indications in the following address locations (7-0), except that these alarm states are latched.
7 6
A Drop Bus Port n TU/VT AIS Alarm: A 1 indicates that an AIS has been detected in the V1/V2 pointer bytes for the TU/VT selected. A Drop Bus Port n Loss Of TU/VT Pointer Alarm: A 1 indicates that a loss of pointer has been detected in the V1/V2 pointer bytes for the TU/VT selected. A Drop Bus Port n TU/VT Pointer Size Error Indication: A 1 indicates that the receive size indicator in the pointer (Bits 5 and 6 in the V1 pointer byte) is not 10 for the TU/VT selected. The detection and recovery time is immediate. A Drop Bus Port n New Data Flag Indication: A 1 indicates that a New Data Flag (1001 or 0001/1101/1011/1000) has been detected in the V1 pointer byte for the TU/VT selected (i.e., bits 1-4 in the V1 byte are the inverse of the normal 0110 pattern or differ in only one bit, with a correct size indicator and a valid pointer value). A Drop Bus Port n Remote Server Defect Indication: A 1 indicates that either a remote server defect alarm has been detected (bits 5, 6 and 7 in K4 (Z7) byte are equal to 101), or an RDI has been detected coming from older equipment (bit 8 in V5 byte equals 1 when bits 6 and 7 in K4 (Z7) byte are equal to 00 or 11). The number of consecutive events used for detection and recovery is determined by control bit V5AL10. A Drop Bus Port n Remote Failure Indication: A 1 indicates that bit 4 in the V5 byte is equal to 1 for the TU/VT selected. The detection and recovery time is immediate.
5
AnSIZE
4
AnNDF
3
AnRDIS
2
AnRFI
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DATA SHEET
Address 031 Port 1 061 Port 2 091 Port 3 0C1 Port 4 (cont.)
Bit 1
Symbol AnUNEQ
Description A Drop Bus Port n Unequipped Indication: A 1 indicates that an Unequipped status has been detected in the V5 signal label (Bits 5-7 in V5 byte = 0) for the TU/VT selected in the A side drop bus. An unequipped signal label is equal to 000. Five or more consecutive received unequipped signal labels will cause this alarm. Recovery occurs when five or more consecutive signal labels are received not equal to 000. A Drop Bus Port n Signal Label Mismatch Indication: A 1 indicates that the receive signal label (Bits 5-7 in V5 byte) does not match the microprocessor-written signal label in the TU/VT selected for the A side drop bus. Five or more consecutive signal label mismatches (against the microprocessor-written value), or received labels not equal to 001, results in an alarm. Recovery occurs upon receipt of five or more consecutive correct signal labels, or 001 values. A Drop Bus Port n Positive Pointer Justification Counter: A four-bit counter that increments on a positive pointer movement for the TU/VT selected. The counter saturates at full count and is cleared when it is read. A Drop Bus Port n Negative Pointer Justification Counter: A four-bit counter that increments on a negative pointer movement for the TU/VT selected. The counter saturates at full count and is cleared when it is read. A Drop Bus Port n BIP-2 Counter: An 8-bit counter which counts the number of BIP-2 errors detected for the TU/VT selected. A maximum of two errors can occur each frame. These two errors cause a single count if the BLOCK control bit is set to 1. The counter saturates at full count and is cleared when it is read. A Drop Bus Port n FEBE Counter: An 8-bit counter which counts the number of FEBE errors received (Bit 3 in V5 byte = 1) for the TU/VT selected. The counter saturates at full count and is cleared when it is read. Unused: These bits read out as indeterminate. A Drop Bus Port n Received Signal Label: These three bit positions correspond to the three signal label bits in bits 5 through 7 of the V5 byte in the TU/VT selected. This location is updated every 500 microseconds. Bit 2 corresponds to bit 7 in the V5 byte. These bits are also compared against the microprocessor-written mismatch signal label bits for an unequipped and mismatch indication. Code 1 (001) has been implemented in hardware and does not have to be written into this location. Same alarms as the corresponding address 04F, 07F, 0AF, 0DF bit positions, except that these alarms are latched. Unused: These bits read out as zero. Same alarms as the corresponding address 04F, 07F, 0AF, 0DF bit positions, except that these alarms are latched. Unused: These bits read out as zero.
0
AnSLER
032 Port 1 062 Port 2 092 Port 3 0C2 Port 4
7-4
AnPJ Counter
3-0
AnNJ Counter
033 Port 1 063 Port 2 093 Port 3 0C3 Port 4 034 Port 1 064 Port 2 094 Port 3 0C4 Port 4 035 Port 1 065 Port 2 095 Port 3 0C5 Port 4
7-0
AnBIP2 Counter
7-0
AnFEBE Counter
7-3 2-0
Unused An Rx Label
04E Port 1 07E Port 2 0AE Port 3 0DE Port 4
7-6 5-4 3-2 1-0
Latched An Alarms Unused Latched An Alarms Unused
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Address 04F Port 1 07F Port 2 0AF Port 3 0DF Port 4
Bit 7
Symbol AnRDIP
Description A Drop Bus Port n Remote Payload Defect Indication: A 1 indicates that a remote payload defect alarm has been detected (bits 5, 6 and 7 in K4 (Z7) byte are equal to 010). The number of consecutive events used for detection and recovery is determined by control bit V5AL10. A Drop Bus Port n Remote Connectivity Defect Indication: A 1 indicates that a remote connectivity defect alarm has been detected (bits 5, 6 and 7 in K4 (Z7) byte are equal to 110). The number of consecutive events used for detection and recovery is determined by control bit V5AL10. Unused: These bits read out as zero. A Drop Bus Port n J2 Loss Of Lock Alarm: Enabled when control bit J2nSIZE is a 0, and control bit J2nCOM is a 1. A 1 indication occurs when the alignment of the 16-byte J2 trace identifier label (message) has not been established. A Drop Bus Port n J2 Trail Trace Mismatch Alarm: Enabled when control bit J2nSIZE is a 0, and control bit J2nCOM is a 1. A 1 indicates that the stable 16-byte message did not match for one message time. Recovery occurs when the J2 state machine loses lock and then acquires lock with a 16-byte stable J2 message that matches the J2 comparison message written by the microprocessor. Unused: These bits read out as zero. A Drop Bus Port n Receive K4 (Z7) Byte: The eight bits in this register position correspond to the K4 (Z7) byte received in the TU/VT selected. Bit 7 corresponds to bit 1 in the K4 (Z7) byte. A Drop Bus Port n Receive O-bits: The two nibbles (bits 7-4 and 3-0) in this register correspond to the two sets of four overhead communication bits received in the TU/VT selected. Bit 7 corresponds to bit 3 in the second justification control byte, while bit 0 corresponds to bit 6 in the first justification control byte. The two nibbles written into this register location will be from the same frame. Same alarms as the following address locations (7-1), except that these alarm states are latched. Unused: This bit reads out as indeterminate.
6
AnRDIC
5-4 3
Unused AnJ2LOL
2
AnJ2TIM
1-0 038 Port 1 068 Port 2 098 Port 3 0C8 Port 4 039 Port 1 069 Port 2 099 Port 3 0C9 Port 4 7-0
Unused An Receive K4 (Z7) Byte An Receive O-Bits
7-0
05A Port 1 08A Port 2 0BA Port 3 0EA Port 4
7-1
Latched An Alarms Unused
0
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Address 05B Port 1 08B Port 2 0BB Port 3 0EB Port 4
Bit 7
Symbol AnTCUQ
Description A Drop Bus Port n Tandem Connection Unequipped Alarm: A TC unequipped alarm indication (a 1) occurs when bits 3 through 8 in the N2 (Z6) byte are all equal to 0 for 5 or more consecutive frames. Recovery to 0 occurs when bits 3 through 8 are not all equal to 0 for 5 or more consecutive frames. A Drop Bus Port n Tandem Connection AIS Alarm: A TC AIS alarm indication (a 1) occurs when bit 4 in the N2 (Z6) byte is equal to 1 for five or more consecutive frames. Recovery to 0 occurs when bit 4 is a 0 for five or more consecutive frames. A Drop Bus Port n Tandem Connection Loss Of Multiframe Alarm: A TC loss of multiframe alarm indication (a 1) occurs when four or more consecutive errored multiframes are detected in bits 7 and 8 in the N2 (Z6) byte. Recovery to 0 occurs when three consecutive non-errored multiframes (1111 1111 1111 1110) are detected. A Drop Bus Port n Bus Tandem Connection Trail Trace Message Loss Of Lock Alarm: An alarm indication (a 1) occurs when the alignment of the 16-byte N2 (Z6) Tandem Connection Trace identifier label (message) has not been established. A Drop Bus Port n Bus Tandem Connection Trail Trace Message Mismatch Alarm: An alarm indication (a 1) indicates that the stable Tandem Connection 16-byte message did not match for one message time. Recovery to 0 occurs when the N2 (Z6) byte TC message state machine loses lock and then acquires lock with a 16-byte stable N2 (Z6) byte message that matches the N2 (Z6) byte comparison message written by the microprocessor. A Drop Bus Port n Tandem Connection ODI Alarm: A TC ODI alarm indication (a 1) occurs when N2 (Z6) byte bit 7 in frame 74 is equal to 1 for five or more consecutive frames. Recovery to 0 occurs when bit 7 is a 0 for five or more consecutive frames. A Drop Bus Port n Tandem Connection RDI Alarm: A TC RDI alarm indication (a 1) occurs when N2 (Z6) byte bit 8 in frame 73 is equal to 1 for five or more consecutive frames. Recovery to 0 occurs when bit 8 is a 0 for five or more consecutive frames. Unused: This bit reads out as indeterminate. A Drop Bus Port n Tandem Connection BIP-2 Counter: An 8-bit counter which counts the number of BIP-2 errors detected in the N2 (Z6) byte for the TU/VT selected when the tandem connection feature is enabled. A maximum of two errors can be counted each frame. These two errors cause a single count if the BLOCK control bit is set to 1. The counter saturates at full count and is cleared when it is read. A Drop Bus Port n Tandem Connection REI Counter: An 8-bit counter which counts the number of REI errors detected in bit 5 in the N2 (Z6) byte for the TU/VT selected when the tandem connection feature is enabled. The counter saturates at full count and is cleared when it is read.
6
AnTCAIS
5
AnTCLM
4
AnTCLL
3
AnTCTM
2
AnTCODI
1
AnTCRDI
0 100 Port 1 200 Port 2 300 Port 3 400 Port 4 7-0
Unused An TC BIP-2 Error Counter
101 Port 1 201 Port 2 301 Port 3 401 Port 4
7-0
An TC REI Error Counter
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Address 102 Port 1 202 Port 2 302 Port 3 402 Port 4 116 Port 1 216 Port 2 316 Port 3 416 Port 4 03A Port 1 06A Port 2 09A Port 3 0CA Port 4 03B Port 1 06B Port 2 09B Port 3 0CB Port 4
Bit 7-0
Symbol An TC OEI Error Counter An Receive V4 Byte
Description A Drop Bus Port n Tandem Connection OEI Counter: An 8-bit counter which counts the number of OEI errors detected in bit 6 in the N2 (Z6) byte for the TU/VT selected when the tandem connection feature is enabled. The counter saturates at full count and is cleared when it is read. A Drop Bus Port n Receive V4 Byte: When control bit V4EN is 1, the eight bits in this register position correspond to the V4 byte received in the TU/VT selected. Bit 7 corresponds to bit 1 in the V4 byte.
7-0
7-0
Latched Bn Same alarms as the following address locations (7-0), except that these Alarms alarm states are latched.
7 6
BnAIS BnLOP
B Drop Bus Port n TU/VT AIS Alarm: A 1 indicates that an AIS has been detected in the V1/V2 pointer bytes for the TU/VT selected. B Drop Bus Port n Loss Of TU/VT Pointer Alarm: A 1 indicates that a loss of pointer has been detected in the V1/V2 pointer bytes for the TU/VT selected. B Drop Bus Port n TU/VT Pointer Size Error Indication: A 1 indicates that the receive size indicator in the pointer (Bits 5 and 6 in the V1 pointer byte) is not 10 for the TU/VT selected. The detection and recovery time is immediate. B Drop Bus Port n New Data Flag Indication: A 1 indicates that a New Data Flag (1001 or 0001/1101/1011/1000) has been detected in the V1 pointer byte for the TU/VT selected (i.e., bits 1-4 in the V1 byte are the inverse of the normal 0110 pattern or differ in only one bit, with a correct size indicator and a valid pointer value). B Drop Bus Port n Remote Server Defect Indication: A 1 indicates that either a remote server defect alarm has been detected (bits 5, 6 and 7 in K4 (Z7) byte are equal to 101), or an RDI has been detected coming from older equipment (bit 8 in V5 byte equals 1 when bits 6 and 7 in K4 (Z7) byte are equal to 00 or 11). The number of consecutive events used for detection and recovery is determined by control bit V5AL10. B Drop Bus Port n Remote Failure Indication: A 1 indicates that bit 4 in the V5 byte is equal to 1 for the TU/VT selected. The detection and recovery time is immediate.
5
BnSIZE
4
BnNDF
3
BnRDIS
2
BnRFI
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Address 03B Port 1 06B Port 2 09B Port 3 0CB Port 4 (cont.)
Bit 1
Symbol BnUNEQ
Description B Drop Bus Port n Unequipped Indication: A 1 indicates that an Unequipped status has been detected in the V5 signal label (Bits 5-7 in V5 byte = 0) for the TU/VT selected in the B side drop bus. An unequipped signal label is equal to 000. Five or more consecutive received unequipped signal labels will cause this alarm. Recovery occurs when five or more consecutive signal labels are received not equal to 000. B Drop Bus Port n Signal Label Mismatch Indication: A 1 indicates that the receive signal label (Bits 5-7 in V5 byte) does not match the microprocessor-written signal label in the TU/VT selected for the B side drop bus. Five or more consecutive signal label mismatches (against the microprocessor-written value), or received labels not equal to 001, results in an alarm. Recovery occurs upon receipt of five or more consecutive correct signal labels, or 001 values. B Drop Bus Port n Positive Pointer Justification Counter: A four-bit counter that increments on a positive pointer movement for the TU/VT selected. The counter saturates at full count and is cleared when it is read. B Drop Bus Port n Negative Pointer Justification Counter: A four-bit counter that increments on a negative pointer movement for the TU/VT selected. The counter saturates at full count and is cleared when it is read. B Drop Bus Port n BIP-2 Counter: An 8-bit counter which counts the number of BIP-2 errors detected for the TU/VT selected. A maximum of two errors can occur each frame. These two errors cause a single count if the BLOCK control bit is set to 1. The counter saturates at full count and is cleared when it is read. B Drop Bus Port n FEBE Counter: An 8-bit counter which counts the number of FEBE errors received (Bit 3 in V5 byte = 1) for the TU/VT selected. The counter saturates at full count and is cleared when it is read. Unused: These bits read out as indeterminate. B Drop Bus Port n Received Signal Label: These three bit positions correspond to the three signal label bits located in bits 5 through 7 of the V5 byte for the TU/VT selected. This location is updated every 500 microseconds. Bit 2 corresponds to bit 7 in the V5 byte. These bits are also compared against the microprocessor-written mismatch signal label bits for an unequipped and mismatch indication. Code 1 (001) has been implemented in hardware and does not have to be written into this location. Same alarms as the corresponding address 05F, 08F, 0BF, 0EF bit positions except that these alarms are latched. Unused: These bits read out as zero. Same alarms as the corresponding address 05F, 08F, 0BF, 0EF bit positions except that these alarms are latched. Unused: These bits read out as zero.
0
BnSLER
03C Port 1 06C Port 2 09C Port 3 0CC Port 4
7-4
BnPJ Counter
3-0
BnNJ Counter
03D Port 1 06D Port 2 09D Port 3 0CD Port 4 03E Port 1 06E Port 2 09E Port 3 0CE Port 4 03F Port 1 06F Port 2 09F Port 3 0CF Port 4
7-0
BnBIP2 Counter
7-0
BnFEBE Counter
7-3 2-0
Unused Bn RX Label
05E Port 1 08E Port 2 0BE Port 3 0EE Port 4
7-6 5-4 3-2 1-0
Latched Bn Alarms Unused Latched Bn Alarms Unused
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Address 05F Port 1 08F Port 2 0BF Port 3 0EF Port 4
Bit 7
Symbol BnRDIP
Description B Drop Bus Port n Remote Payload Defect Indication: A 1 indicates that a remote payload defect alarm has been detected (bits 5, 6 and 7 in K4 (Z7) byte are equal to 010). The number of consecutive events used for detection and recovery is determined by control bit V5AL10. B Drop Bus Port n Remote Connectivity Defect Indication: A 1 indicates that a remote connectivity defect alarm has been detected (bits 5, 6 and 7 in K4 (Z7) byte are equal to 110). The number of consecutive events used for detection and recovery is determined by control bit V5AL10. Unused: These bits read out as zero. B Drop Bus Port n J2 Loss Of Lock Alarm: Enabled when control bit J2nSIZE is a 0, and control bit J2nCOM is a 1. A 1 indication occurs when the alignment of the 16-byte J2 trace identifier label (message) has not been established. B Drop Bus Port n J2 Trail Trace Mismatch Alarm: Enabled when control bit J2nSIZE is a 0, and control bit J2nCOM is a 1. A 1 indicates that the stable 16-byte message did not match for one message time. Recovery occurs when the J2 state machine loses lock and then acquires lock with a 16-byte stable J2 message that matches the J2 comparison message written by the microprocessor. Unused: These bits read out as zero.
6
BnRDIC
5-4 3
Unused BnJ2LOL
2
BnJ2TIM
1-0 042 Port 1 072 Port 2 0A2 Port 3 0D2 Port 4 043 Port 1 073 Port 2 0A3 Port 3 0D3 Port 4 7-0
Unused
Bn Receive B Drop Bus Port n Receive K4 (Z7) Byte: The eight bits in this register position correspond to the K4 (Z7) byte received for the TU/VT selected. K4 (Z7) Bit 7 corresponds to bit 1 in the K4 (Z7) byte. Byte Bn Receive B Drop Bus Port n Receive O-bits: The two nibbles (bits 7-4 and 3-0) in this register correspond to the two sets of four overhead communicaO-Bits tion bits received in the TU/VT selected. Bit 7 corresponds to bit 3 in the second justification control byte, while bit 0 corresponds to bit 6 in the first justification control byte. The two nibbles written into this register location will be from the same frame. Latched Bn Alarms Unused Same alarms as the following address locations (7-1), except that these alarm states are latched. Unused: This bit reads out as indeterminate.
7-0
05C Port 1 08C Port 2 0BC Port 3 0EC Port 4
7-1
0
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Address 05D Port 1 08D Port 2 0BD Port 3 0ED Port 4
Bit 7
Symbol BnTCUQ
Description B Drop Bus Port n Tandem Connection Unequipped Alarm: A TC unequipped alarm indication (a 1) occurs when bits 3 through 8 in the N2 (Z6) byte are all equal to 0 for 5 or more consecutive frames. Recovery to 0 occurs when bits 3 through 8 are not all equal to 0 for 5 or more consecutive frames. B Drop Bus Port n Tandem Connection AIS Alarm: A TC AIS alarm indication (a 1) occurs when bit 4 in the N2 (Z6) byte is equal to 1 for five or more consecutive frames. Recovery to 0 occurs when bit 4 is a 0 for five or more consecutive frames. B Drop Bus Port n Tandem Connection Loss Of Multiframe Alarm: A TC loss of multiframe alarm indication (a 1) occurs when four or more consecutive errored multiframes are detected in bits 7 and 8 in the N2 (Z6) byte. Recovery to 0 occurs when three consecutive non-errored multiframes (1111 1111 1111 1110) are detected. B Drop Bus Port n Bus Tandem Connection Trail Trace Message Loss Of Lock Alarm: An alarm indication (a 1) occurs when the alignment of the 16-byte N2 (Z6) Tandem Connection Trace identifier label (message) has not been established. B Drop Bus Port n Bus Tandem Connection Trail Trace Message Mismatch Alarm: An alarm indication (a 1) indicates that the stable Tandem Connection 16-byte message did not match for one message time. Recovery to 0 occurs when the N2 (Z6) byte TC message state machine loses lock and then acquires lock with a 16-byte stable N2 (Z6) byte message that matches the N2 (Z6) byte comparison message written by the microprocessor. B Drop Bus Port n Tandem Connection ODI Alarm: A TC ODI alarm indication (a 1) occurs when N2 (Z6) byte bit 7 in frame 74 is equal to 1 for five or more consecutive frames. Recovery to 0 occurs when bit 7 is a 0 for five or more consecutive frames. B Drop Bus Port n Tandem Connection RDI Alarm: A TC RDI alarm indication (a 1) occurs when N2 (Z6) byte bit 8 in frame 73 is equal to 1 for five or more consecutive frames. Recovery to 0 occurs when bit 8 is a 0 for five or more consecutive frames. Unused: This bit reads out as indeterminate. B Drop Bus Port n Tandem Connection BIP-2 Counter: An 8-bit counter which counts the number of BIP-2 errors detected in the N2 (Z6) byte for the TU/VT selected when the tandem connection feature is enabled. A maximum of two errors can be counted each frame. These two errors cause a single count if the BLOCK control bit is set to 1. The counter saturates at full count and is cleared when it is read. B Drop Bus Port n Tandem Connection REI Counter: An 8-bit counter which counts the number of REI errors detected in bit 5 in the N2 (Z6) byte for the TU/VT selected when the tandem connection feature is enabled. The counter saturates at full count and is cleared when it is read.
6
BnTCAIS
5
BnTCLM
4
BnTCLL
3
BnTCTM
2
BnTCODI
1
BnTCRDI
0 180 Port 1 280 Port 2 380 Port 3 480 Port 4 7-0
Unused Bn TC BIP-2 Error Counter
181 Port 1 281 Port 2 381 Port 3 481 Port 4
7-0
Bn TC REI Error Counter
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Address 182 Port 1 282 Port 2 382 Port 3 482 Port 4 196 Port 1 296 Port 2 396 Port 3 496 Port 4 044 Port 1 074 Port 2 0A4 Port 3 0D4 Port 4
Bit 7-0
Symbol Bn TC OEI Error Counter Bn Receive V4 Byte RnFFE Unused
Description B Drop Bus Port n Tandem Connection OEI Counter: An 8-bit counter which counts the number of OEI errors detected in bit 6 in the N2 (Z6) byte for the TU/VT selected when the tandem connection feature is enabled. The counter saturates at full count and is cleared when it is read. B Drop Bus Port n Receive V4 Byte: When control bit V4EN is 1, the eight bits in this register position correspond to the V4 byte received in the TU/VT selected. Bit 7 corresponds to bit 1 in the V4 byte. Same alarms as the corresponding address 045, 075, 0A5 and 0D5 bits, except that these alarm states are latched. Unused: This bit reads out as 0.
7-0
7 6 5-0
Latched Tx Same alarms as the corresponding address 045, 075, 0A5 and 0D5 bits, Alarms except that these alarm states are latched. RnFFE Receive Port n FIFO Error: A 1 indicates that the receive FIFO for port 1 has overflowed or underflowed. The FIFO is reset automatically. Other than an alarm indication, no action is taken. Unused: This bit reads out as 0. PRBS Analyzer Out of Lock: A 1 indicates that the internal PRBS Analyzer is out of lock. Transmit A Add Bus Port n FIFO Error: A 1 indicates that the A Add bus FIFO has overflowed or underflowed. The FIFO is recentered and is held reset for up to two multiframes automatically. The VT AIS payload will be transmitted via the add bus when the FIFO error occurs. Transmit B Add Bus Port n FIFO Error: A 1 indicates that the B Add bus FIFO has overflowed or underflowed. The FIFO is recentered and is held reset for up to two multiframes automatically. The VT AIS payload will be transmitted via the add bus when the FIFO error occurs. Transmit Port n Loss Of Signal: An alarm occurs when there are no signal transitions detected on the positive rail or negative rail for a period of 256 consecutive pulse positions. Recovery occurs when there are at least 32 transitions counted for 256 consecutive pulse positions. For an NRZ signal, this alarm is active when a low occurs on the external transmit loss of signal indication lead TLOSn, which is shared with the TNIn lead. Transmit Port n Loss Of Clock: A 1 indicates that the transmit clock (TCIn) for port n has stuck high or low for 6 or more clock cycles. Recovery occurs on the first clock transition. Transmit Port n AIS Detected: A 1 indicates that line AIS (one or less zero in 256 bits) has been detected in the bit stream for port n. Recovery occurs when there are 3 or more zeros in 256 bits. Other than reporting the alarm, no action is taken.
045 Port 1 075 Port 2 0A5 Port 3 0D5 Port 4
7
6 5 4
Unused ANAnOOL TAnFE
3
TBnFE
2
TnLOS
1
TnLOC
0
TnDAIS
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Address 046 Port 1 076 Port 2 0A6 Port 3 0D6 Port 4
Bit 7-0
Symbol Coding Violation Counter Low Order Byte
Description Transmit Port n Coding Violation Counter: Low order byte of a 16-bit saturating counter which counts the number of coding errors that have occurred in the HDB3 line code. During a read cycle, internal logic holds any new count until the read cycle is complete, and then the counter is updated. This counter is cleared on a reset pulse, any RESET, RnSETS or RnSETC control bit = 1, or when its low order byte is read. This low order byte must be read before the high order byte for the same port, which is located in the following address. Transmit Port n Coding Violation Counter: High order byte of an 16-bit saturating counter which counts the number of coding errors that have occurred in the HDB3 line codes. During a read cycle, internal logic holds any new count until the read cycle is complete, and then the counter is updated. This counter is cleared on a reset pulse, any RESET, RnSETS or RnSETC control bit = 1, or when its low order byte is read. This high order byte must be read after the low order byte for the same port, which is located in the preceding address, but before the next read of the low order byte for any port. (Reading the low order byte for any port causes a simultaneous transfer of the contents of the high order byte for the same port into a high order byte memory location that is common to all four ports. When any high order byte is read, the data output from the high order byte address is the content of this common memory location, not the current content of the addressed high order byte.)
047 Port 1 077 Port 2 0A7 Port 3 0D7 Port 4
7-0
Coding Violation Counter High Order Byte
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PORT n - OPERATION REGISTER DESCRIPTIONS Address 048 Port 1 078 Port 2 0A8 Port 3 0D8 Port 4 Bit 7-5 4 Symbol Unused 1BnRDI Description Unused: These bits must be written to 0.
QE1M TXC-04252
1-Bit/3-Bit RDI Selection for Port n: When set to 0, the selected port will function as a 3-Bit enhanced RDI. When set to a 1, the selected port will function as 1-Bit RDI. J2 Transmit Message Enable for Port n: A 1 enables a microprocessor-written message to be transmitted. A 0 disables the transmission of the J2 message from RAM. Instead, the J2 byte is transmitted as 00H. J2 Message Size Segment for Port n: Works in conjunction with the J2nCOM bit according to the following table: J2nSIZE 0 J2nCOM 0 Action Transmit and receive J2 message segments are configured for a 16-byte message size. Microprocessor reads 16-byte segment. J2 comparison circuit and alarms are disabled. Transmit and receive J2 message segments are configured for a 16-byte message size. Trail Trace message comparison circuit enabled. Transmit and receive J2 message segments are configured for a 64-byte message size. Microprocessor reads 64-byte segment. J2 comparison circuit and alarms are disabled. The Tandem Connection feature must be disabled by setting TCnEN=0.
3
J2nTEN
2
J2nSIZE
0
1
1
X
1 0
J2nCOM J2nAISE
J2 Message Comparison Enable Bit for Port n: Works in conjunction with the J2nSIZE control bit according to the table given above. J2 AIS/RDI/TC Alarm Enable for Port n: A 1 enables Receive E1 AIS, a Remote Connectivity Defect Indication, and both of the TC alarms (TCnODI, TCnRDI) to be transmitted when either an AnJ2TIM/BnJ2TIM or an AnJ2LOL/BnJ2LOL occurs. The AIS, RDI and TC alarm generated depend on the bus side selected.
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QE1M TXC-04252
DATA SHEET
Address 050 Port 1 080 Port 2 0B0 Port 3 0E0 Port 4
Bit 7
Symbol FnLBK
Description Facility Loopback: A 1 enables an E1 facility (side) loopback for port n. The E1 transmit clock and data output signals are looped back internally as the E1 receive clock and data input signals. The external E1 receive input signals are disabled. The E1 transmit clock and data output signals are provided at the interface. Line Loopback: A 1 enables an E1 line (side) loopback for port n. The receive E1 clock and data output signals are looped back internally as the E1 transmit input signals. The external E1 transmit clock and data input signals are disabled. The E1 receive clock and data output signals are provided at the interface. Send Receive E1 Line AIS for Port n: A 1 enables an E1 AIS (unframed all ones signal) to be inserted into the receive data stream for port n independent of the status of the internal alarms. Transmit E1 Line AIS for Port n: A 1 enables an E1 AIS (unframed all ones signal) to be inserted into the transmit data stream for port n independent of the status of the internal alarms. Transmit VT AIS for the TU/VT Selected for Port n: A 1 enables a TU/VT AIS to be transmitted for the TU/VT selected. A TU/VT AIS consists of all ones in the entire TU/VT, including bytes V1 through V4. Transmit Port n RFI (Remote Failure Indication): A 1 enables an RFI alarm to be transmitted (bit 4 in the V5 byte is set to 1). Transmit Port n RDIS (Remote Server Defect Indication): A 1 enables an RDIS to be transmitted (bit 8 in the V5 byte is set to 1, and bits 5, 6 and 7 in the K4 (Z7) byte are set to 101). Transmit Port n RDIP (Remote Payload Defect Indication): A 1 enables an RDIP to be transmitted (bit 8 in the V5 byte is set to 0, and bits 5, 6 and 7 in the K4 (Z7) byte are set to 010).
6
LnLBK
5
RnAIS
4
TnAIS
3
TnVTAIS
2 1
TnRFI TnRDIS
0
TnRDIP
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DATA SHEET
QE1M TXC-04252
Address 051 Port 1 081 Port 2 0B1 Port 3 0E1 Port 4
Bit 7 6 5 4
Symbol TCnRDI TCnODI TCnAIS TCnEN
Description Tandem Connection RDI Generation for Port n: A 1 enables a TC RDI to be generated (bit 8 in frame 73 is a 1). Tandem Connection ODI Generation for Port n: A 1 enables a TC ODI to be generated (bit 7 in frame 74 is a 1). Tandem Connection AIS Indication Transmitted for Port n: A 1 enables a TC AIS indication to be generated (bit 4 in the N2 (Z6) byte is a 1). Tandem Connection Feature Enable for Port n: A 1 enables the TU Tandem Connection Feature (J2nSIZE must be 0). A 0 disables the tandem connection feature. In the receive direction all TC alarms are disabled. In the transmit direction, bits 3 through 8 in the N2(Z6) byte are transmitted as 0 while bits 1 and 2 still contain the calculated BIP-2. Tandem Connection Remote Defect Indication Enable for Port n: As explained in Note1, a 1 enables internal defined tandem connection alarms to send a TC RDI (bit 8 in frame 73). For example, a TC RDI for port 1 is generated: - When TC enable (TC1EN) and TC RDI enable (TC1RE) are 1 and any of: - Loss Of Pointer Alarm (A1LOP B1LOP) , - TU AIS Alarm (A1AIS, B1AIS) - Drop Bus AIS Alarm (AsUASI, BsUASI) when HEAISE is 1 - Drop Bus H4 Alarm (AsDH4E, BsDH4E) when DV1SEL is 1 - Unequipped signal label (A1UNEQ, B1UNEQ) when UQAE is 1 - Mismatch signal label (A1SLER, B1SLER) - J2 Loss Of Lock Alarm (A1J2LOL, B1J2LOL) when J2AISEN is 1 - J2 Mismatch Alarm (A1J2TIM, B1J2TIM) when J2AISEN is 1 - TC Unequipped Alarm (A1TCUQ, B1TCUQ) - TC Loss Of Lock Alarm (A1TCLL, B1TCLL) - TC Mismatch Alarm (A1TCTM, B1TCTM) - TC Loss Of Multiframe Alarm (A1TCLM, B1TCLM) - A 1 written to TC1RDI - When TC enable (TC1EN) is a 1 and TC RDI enable (TC1RE) is 0 and: - A 1 written to TC1RDI.
3
TCnRE
Note 1: In determining whether to send TC ODI or TC RDI, it is necessary to sample certain alarm conditions. Since TC ODI or TC RDI are sent only once for every 38 ms multiframe, it is conceivable that these alarms may toggle more than one time in this interval. Therefore, all the alarms needed to generate TC ODI or TC RDI are sampled during every 500 s multiframe, setting the TC ODI or TC RDI alarm.
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QE1M TXC-04252
DATA SHEET
Address 051 Port 1 081 Port 2 0B1 Port 3 0E1 Port 4 (cont.)
Bit 2
Symbol TCnOE
Description Tandem Connection Outgoing Defect Indication Enable for Port n: As explained in Note 1, a 1 enables internal defined tandem connection alarms to send a TC ODI (bit 7 in frame 74). For example, a TC ODI for port 1 is generated: - When TC enable (TC1EN) and TC ODI enable (TC1OE) are 1 and any of: - Loss Of Pointer Alarm (A1LOP B1LOP) , - TU AIS Alarm (A1AIS, B1AIS) - Drop Bus AIS Alarm (AsUASI, BsUASI) when HEAISE is 1 - Drop Bus H4 Alarm (AsDH4E, BsDH4E) when DV1SEL is 1 - Unequipped signal label (A1UNEQ, B1UNEQ) when UQAE is 1 - Mismatch signal label (A1SLER, B1SLER) - J2 Loss Of Lock Alarm (A1J2LOL, B1J2LOL) when J2AISEN is 1 - J2 Mismatch Alarm (A1J2TIM, B1J2TIM) when J2AISEN is 1 - TC Unequipped Alarm (A1TCUQ, B1TCUQ) - TC AIS alarm (A1TCAIS, B1TCAIS) - TC Loss Of Lock Alarm (A1TCLL, B1TCLL) - TC Mismatch Alarm (A1TCTM, B1TCTM) - TC Loss Of Multiframe Alarm (A1TCLM, B1TCLM) - A 1 written to TC1ODI. (where S is the STS-1 or AU-3 identifier, 1-3) - When TC enable (TC1EN) is a 1 and TC ODI enable (TC1OE) is 0 and: - A 1 written to TC1ODI.
1 0
TCnAEN TnRDIC
Tandem Connection Line AIS Enable for Port n: A 1 enables internal receive TC alarms to generate receive E1 line AIS. Transmit Port n RDIC (Remote Connectivity Defect Indication): A 1 enables an RDIC to be transmitted (bit 8 in the V5 byte is set to 1, and bits 5, 6 and 7 in the K4 (Z7) byte are set to 110). Reset Port n Selected Functions: A 1 will clear the alarms, reset the performance counters to 0, and re-initialize the FIFOs associated with port n. The control bits for port n are not reset. This bit is self-clearing, and will reset to 0 after the reset cycle is completed. Reset Port n Performance Counters: A 1 resets the performance counters to 0 for port n. This bit is self-clearing, and will reset to 0 after the reset cycle is completed. Unused: These bits must be written to 0. Transmit Port n BIP-2 Error Mask (Force BIP-2 Error): A 1 causes bits 1 and 2 (the BIP-2 value) in the V5 byte to be inverted from the calculated value and transmitted for one frame. This bit is self-clearing, and will reset to 0 after the single error is transmitted.
052 Port 1 082 Port 2 0B2 Port 3 0E2 Port 4
7
RnSETS
6
RnSETC
5-2 1
Unused TnFB2
Note 1: In determining whether to send TC ODI or TC RDI, it is necessary to sample certain alarm conditions. Since TC ODI or TC RDI are sent only once for every 38 ms multiframe, it is conceivable that these alarms may toggle more than one time in this interval. Therefore, all the alarms needed to generate TC ODI or TC RDI are sampled during every 500 s multiframe, setting the TC ODI or TC RDI alarm.
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DATA SHEET
QE1M TXC-04252
Address 052 Port 1 082 Port 2 0B2 Port 3 0E2 Port 4 (cont.) 053 Port 1 083 Port 2 0B3 Port 3 0E3 Port 4
Bit 0
Symbol TnFFB
Description Transmit Port n FEBE Error Mask (Force FEBE Error): A 1 causes bit 3 (the FEBE value) of the V5 byte to be transmitted as a 1. This control bit is self-clearing, and will reset to 0 after the V5 byte has been transmitted. Please note that if a FEBE is being sent as a result of a receive BIP-2 error, the FEBE error set by this bit is transmitted afterwards. Unused: These bits must be written to 0. A Drop Bus Port n Microprocessor-Written Signal Label: The three bit positions correspond to the three signal label bits found in bits 5 through 7 in the V5 byte for the TU/VT selected. Bit 2 in this register corresponds to bit 7 in the V5 byte. The bits written into this register are compared against the received signal for a mismatch signal label alarm. Unused: These bits must be written to 0. B Drop Bus Port n Microprocessor-Written Signal Label: The three bit positions correspond to the three signal label bits found in bits 5 through 7 in the V5 byte for the TU/VT selected. Bit 2 in this register corresponds to bit 7 in the V5 byte. The bits written into this register are compared against the received signal for a mismatch signal label alarm. Unused: These bits must be written to 0. Transmit Port n Signal Label: The three bit positions correspond to the three signal label bits found in bits 5 through 7 in the V5 byte for the TU/VT selected for transmission. Bit 2 in this register corresponds to bit 7 in the V5 byte.
7-3 2-0
Unused AnUPSL
054 Port 1 084 Port 2 0B4 Port 3 0E4 Port 4
7-3 2-0
Unused BnUPSL
055 Port 1 085 Port 2 0B5 Port 3 0E5 Port 4 058 Port 1 088 Port 2 0B8 Port 3 0E8 Port 4
7-3 2-0
Unused Tn TX Label
7-4
Transmit Transmit K4 (Z7) Value Port n: The value written into bits 7, 6, 5, 4 and 0 in this register is transmitted when control bit TOBWZ is 0. Bits 3, 2, and 1 K4 (Z7) Byte Value are assigned for the RDI indicators and cannot be written to in this register. Bit 7 corresponds to bit 1 in the K4 (Z7) byte. Unused Unused: These bits must be written to 0. Transmit Transmit K4 (Z7) Value Port n: The value written into bits 7, 6, 5, 4 and 0 in this register is transmitted when control bit TOBWZ is 0. Bits 3, 2, and 1 K4 (Z7) Byte Value are assigned for the RDI indicators and cannot be written to in this register. Bit 0 corresponds to bit 8 in the K4 (Z7) byte. Transmit O-bits Transmit O Bits Port n: The value written into this register is transmitted when control bit TOBWZ is 0. Bits 7 through 4 correspond to bits 3 through 6 in the second justification control byte. Bits 3 through 0 correspond to bits 3 through 6 in the first justification control byte. Transmit V4 Byte Port n: The value written into this register will be transmitted as the V4 byte. Bits 7-0 of the register correspond to bits 1-8 of the V4 byte.
3-1 0
059 Port 1 089 Port 2 0B9 Port 3 0E9 Port 4 511 Port 1 591 Port 2 611 Port 3 691 Port 4
7-0
7-0
Transmit V4 Byte
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QE1M TXC-04252
DATA SHEET
PORT n - A AND B DROP J2 AND N2 (Z6) MESSAGE SEGMENTS Address 140 Port 1 240 Port 2 340 Port 3 440 Port 4 to 17F Port 1 27F Port 2 37F Port 3 47F Port 4 Bit 7-0 Symbol A Side Receive J2 and N2 (Z6) Message Segments Description A Side Drop J2 and N2 (Z6) Message Segments: The following locations store the received 64-byte J2 message when control bit J2nSIZE is a 1, and the received 16-byte J2 message, and microprocessor-written 16-byte J2 message when J2nSIZE is a 0, and the received 16-byte N2 (Z6) trail trace message and microprocessor-written 16-byte N2 (Z6) message used for message mismatch. Location X40-X7F Message Segment J2 Message size configured for 64 bytes. The 64-byte message is written into memory with no specific starting address location. The N2 (Z6) tandem connection feature is disabled. Received 16-byte J2 message segment. Microprocessor-written 16-byte J2 message segment. The starting address of the message must be written to location X50 (multiframe value of 1). Received 16-byte N2 (Z6) message segment. Microprocessor-written 16-byte N2 (Z6) message segment. The starting address of the message must be written to location X70 (multiframe value of 1).
X40-X4F X50-X5F
X60-X6F X70-X7F
1C0 Port 1 2C0 Port 2 3C0 Port 3 4C0 Port 4 to 1FF Port 1 2FF Port 2 3FF Port 3 4FF port 4
7-0
B Side Receive J2 and N2 (Z6) Message Segments
B Side Drop J2 and N2 (Z6) Message Segments: The following locations store the received 64-byte J2 message when control bit J2nSIZE is a 1, and the received 16-byte J2 message, and microprocessor-written 16-byte J2 message when J2nSIZE is a 0, and the received 16-byte N2 (Z6) trail trace message and microprocessor-written 16-byte N2 (Z6) message used for message mismatch. Location XC0-XFF Message Segment J2 Message size configured for 64 bytes. The 64-byte message is written into memory with no specific starting address location. The N2 (Z6) tandem connection feature is disabled. Received 16-byte J2 message segment. Microprocessor-written 16-byte J2 message segment. The starting address of the message must be written to location XD0 (multiframe value of 1). Received 16-byte N2 (Z6) message segment. Microprocessor-written 16-byte N2 (Z6) message segment. The starting address of the message must be written to location XF0 (multiframe value of 1).
XC0-XCF XD0-XDF
XE0-XEF XF0-XFF
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DATA SHEET
QE1M TXC-04252
Address 540 Port 1 5C0 Port 2 640 Port 3 6C0 Port 4 to 57F Port 1 5FF Port 2 67F Port 3 6FF Port 4
Bit 7-0
Symbol Transmit J2 and N2 (Z6) Message Segments
Description Transmit J2 and N2 (Z6) Message Segments: The following locations store the transmitted 64-byte J2 message when control bit J2nSIZE is a 1, and the transmitted 16-byte J2 and N2 (Z6) messages when J2nSIZE is a 0. Location 540-57F (Port 1) 5C0-5FF (Port 2) 640-67F (Port 3) 6C0-6FF (Port 4) 540-54F (Port 1) 5C0-5CF (Port 2) 640-64F (Port 3) 6C0-6CF (Port 4) 560-56F (Port 1) 5E0-5EF (Port 2) 660-66F (Port 3) 6E0-6EF (Port 4) Message Segment J2 Message size configured for 64 bytes. The 64-byte message is transmitted from no specific starting address. The tandem connection feature is disabled. J2 Message size configured for 16 bytes. The 16-byte message is transmitted with no specific starting address. N2 (Z6) Message size configured for 16 bytes. The 16-byte message is transmitted with no specific starting address.
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QE1M TXC-04252 PACKAGE INFORMATION
DATA SHEET
The QE1M device is packaged in two formats. One is a 160-lead plastic quad flat package (PQFP) suitable for surface mounting, as illustrated in Figure 28.
120 121
81 80
See Details "B" and "C"
TRANSWITCH
TXC-04252AIPQ
0.65(TYP) Detail "B" 0.20(MIN) 0.40(MAX) 160 1 INDEX LEAD #1 25.35 (SQ) 28.00 (SQ) 31.20 (SQ) 40 41 Detail "C"
(TYP)
4.07 (MAX) SEE DETAIL "A" 0.15 0.25 (MIN)
3.67
0 -10 DEGREES
DETAIL "A"
0.88
Notes: 1. All linear dimensions are in millimeters. 2. All dimensions are nominal unless otherwise indicated.
Figure 28. QE1M TXC-04252 160-Lead Plastic Quad Flat Package
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DATA SHEET
QE1M TXC-04252
The other is a 208-lead plastic ball grid array package (PBGA) suitable for surface mounting, as illustrated in Figure 29.
E E2 Bottom View -E1-
TRANSWITCH
TXC-04252AIOG
D D2 E1/4 Note 2
D1/4
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 TRPNMLKJHGFEDCBA
-D1-
A3
A2
A A1
e
b
Dimension (Note 1) Notes: 1. All dimensions are in millimeters. Values shown are for reference only. 2. Identification of the solder ball A1 corner is contained within this shaded zone. This package corner may be a 90 angle, or chamfered for A1 identification. 3. Size of array: 16 x 16, JEDEC code MO-151-AAF-1 A A1 A2 A3 (Ref.) b D D1 (BSC) D2 E E1 (BSC) E2 e (BSC)
Min 1.35 0.30 0.75 0.36 0.40 17.00 15.00 15.00 17.00 15.00 15.00 1.00
Max 1.75 0.50 0.85 0.60
15.70
15.70
Figure 29. QE1M TXC-04252 208-Lead Plastic Ball Grid Array Package
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QE1M TXC-04252 ORDERING INFORMATION
Part Number:
DATA SHEET
TXC-04252AIPQ TXC-04252AIOG
160-lead plastic quad flat package (PQFP) 208-lead plastic ball grid array package (PBGA)
RELATED PRODUCTS
TXC-02302B, SYN155C VLSI Device (155-Mbit/s Synchronizer, Clock and Data Output). Provides complete STS-3/STM-1 frame synchronization on incoming 155 Mbit/s signals in a single low power CMOS unit. It has both clock and data outputs on the line side. TXC-03001B, SOT-1 VLSI Device (SONET STS-1 Overhead Terminator). In a single device, it provides the SONET interface to any payload. Provides access to all of the transport and path overhead defined for an STS-1/STS-N SONET signal. TXC-03003B, SOT-3 VLSI Device (STM-1/STS-3/STS-3c Overhead Terminator). This device performs section, line, and path overhead processing for a STS-3/STS-3c/STM-1 signal. Compliant with ANSI and ITU-TSS standards. TXC-03011, SOT-1E VLSI Device (SONET STS-1 Overhead Terminator). In a single device, it provides the SONET interface to any payload. It provides access to all of the transport and path overhead defined for an STS-1/STS-N SONET signal. This device has extended features relative to the TXC-03001B that use more input/output pins. It has a larger package. TXC-04002B, ADMA-E1 Device (2 Mbit/s to TU-12 Async Mapper-Desync). Interconnects two E1 signals with any two asynchronous mode TU-12 tributaries carried in an SDH VC-4 formatted bus at the STM-1 byte rate. This is a functionally enhanced version of the TXC-04002 device, and it is also a two-channel predecessor of the QE1M four-channel device. TXC-04216, E1Mx16 VLSI Device (Sixteen channel E1 to AU-4/VT2 or TU-12 Async Mapper-Desync) - E1Mx16 is a module containing four QE1M chips. It interconnects sixteen E1 signals with any sixteen asynchronous mode VT2 or TU-12 tributaries carried in SDH AU-4/AU-3 rate payload interface. TXC-06101, PHAST-1 VLSI Device (SONET STS-1 Overhead Terminator). This device provides features similar to those of the TXC-03011 SOT-1E device, but it operates from a power supply of 3.3 volts rather than 5 volts. TXC-06103, PHAST-3N VLSI Device (SONET STM-1, STS-3 or STS-3c Overhead Terminator). This PHAST-3N VLSI device provides a Telecom Bus interface for downstream devices. It operates from a power supply of 3.3 volts.
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DATA SHEET STANDARDS DOCUMENTATION SOURCES
QE1M TXC-04252
Telecommunication technical standards and reference documentation may be obtained from the following organizations:
ANSI (U.S.A.): American National Standards Institute 11 West 42nd Street New York, New York 10036 The ATM Forum (U.S.A., Europe, Asia): 2570 West El Camino Real Suite 304 Mountain View, CA 94040 ATM Forum Europe Office Av. De Tervueren 402 1150 Brussels Belgium ATM Forum Asia-Pacific Office Hamamatsu-cho Suzuki Building 3F 1-2-11, Hamamatsu-cho, Minato-ku Tokyo 105-0013, Japan Bellcore (See Telcordia) CCITT (See ITU-T) EIA (U.S.A.): Electronic Industries Association Global Engineering Documents 7730 Carondelet Avenue, Suite 407 Clayton, MO 63105-3329 ETSI (Europe): European Telecommunications Standards Institute 650 route des Lucioles 06921 Sophia Antipolis Cedex France Tel: 4 92 94 42 22 Fax: 4 92 94 43 33 Web: www.etsi.org Tel: (800) 854-7179 (within U.S.A.) Tel: (314) 726-0444 (outside U.S.A.) Fax: (314) 726-6418 Web: www.global.ihs.com Tel: 3 3438 3694 Fax: 3 3438 3698 Tel: 2 761 66 77 Fax: 2 761 66 79 Tel: (650) 949-6700 Fax: (650) 949-6705 Web: www.atmforum.com Tel: (212) 642-4900 Fax: (212) 302-1286 Web: www.ansi.org
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QE1M TXC-04252
DATA SHEET
GO-MVIP (U.S.A.): The Global Organization for Multi-Vendor Integration Protocol (GO-MVIP) 3220 N Street NW, Suite 360 Washington, DC 20007 ITU-T (International): Publication Services of International Telecommunication Tel: 22 730 5111 Union Telecommunication Standardization Sector Fax: 22 733 7256 Place des Nations, CH 1211 Web: www.itu.int Geneve 20, Switzerland MIL-STD (U.S.A.): DODSSP Standardization Documents Ordering Desk Building 4 / Section D 700 Robbins Avenue Philadelphia, PA 19111-5094 PCI SIG (U.S.A.): PCI Special Interest Group 2575 NE Kathryn Street #17 Hillsboro, OR 97124 Tel: (800) 433-5177 (within U.S.A.) Tel: (503) 693-6232 (outside U.S.A.) Fax: (503) 693-8344 Web: www.pcisig.com Tel: (215) 697-2179 Fax: (215) 697-1462 Web: www.dodssp.daps.mil Tel: (800) 669-6857 (within U.S.A.) Tel: (903) 769-3717 (outside U.S.A.) Fax: (508) 650-1375 Web: www.mvip.org
Telcordia (U.S.A.): Telcordia Technologies, Inc. Attention - Customer Service 8 Corporate Place Piscataway, NJ 08854 TTC (Japan): TTC Standard Publishing Group of the Telecommunications Technology Committee 2nd Floor, Hamamatsu-cho Suzuki Building, 1 2-11, Hamamatsu-cho, Minato-ku, Tokyo Tel: 3 3432 1551 Fax: 3 3432 1553 Web: www.ttc.or.jp Tel: (800) 521-CORE (within U.S.A.) Tel: (908) 699-5800 (outside U.S.A.) Fax: (908) 336-2559 Web: www.telcordia.com
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DATA SHEET LIST OF DATA SHEET CHANGES
QE1M TXC-04252
This change list identifies those areas within this updated QE1M Data Sheet that have significant differences relative to the previous and now superseded QE1M Data Sheet. Updated QE1M Data Sheet: Previous QE1M Data Sheet: Edition 3, December 2000 Edition 2, October 1997
The page numbers indicated below of this updated Data Sheet include significant changes relative to the previous data sheet.
Page Number of Updated Data Sheet All All 1 2-3 9 10 11-20 12 16 20 21 26-30 35-40 38-41 42 47-48 50 51 61
Summary of the Change Added TranSwitch document proprietary markings. Changed edition number and date. Changed `Pin' to `Lead' throughout entire document. Added PBGA package option to last bullet item of Features list. Added to list of Patents. Updated Table of Contents and List of Figures. Modified Note and title of Figure 3. Added Figure 4. Added new column `208-Lead PBGA Lead No.' and changed column heading `Lead No.' to `160-Lead PQFP Lead No.' in all tables. Changed `I/O' to `Input/Output' in table footnote. Changed last sentence of Name/Function column for Symbol MUX. Added second sentence to Name/Function column for Symbol TRS. Modified first and second tables. Moved first row from last table to first table and added Note 3. Modified Note 2. Modified table in Figure 6. Added DPAR and APAR to Figures 7 and 8. Added APAR to Figures 9 and 10. Added address and data signal labels to tables in Figures 13, 14, 15 and 16. Modified waveforms, tables and Notes 3 and 4 in Figures 15 and 16. Modified waveform and table in Figure 17. Added `Unequipped Operation' section. Changed `X' to `0' in first and second rows for DV1REF column. Changed `SLER' to `SLER5' in first column of table and added Note 5. Added new paragraph under `Remote Defect Indications' heading. Modified second heading title and title of table. Switched the position of the words connectivity and payload in the third line of the second paragraph. Made changes in text.
62-67
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QE1M TXC-04252
DATA SHEET
Page Number of Updated Data Sheet 78 80 84 86-92 104 107 110 121 131 133 138, 140 139 140 141-142 143-144 147
Summary of the Change Changed first column of second table. Modified last sentence in second paragraph. Added `Boundary Scan Reset' section. Added column for PBGA and its Lead No. Changed related Comments to include PBGA lead numbers. Added `1BnRDI' for Bit 4 column in first row of first table. Modified Description column for Symbol ABD. Modified Description column for Bits 6 and 4 of Address 013. Modified Description column for Address 0F5, Bit 7. Added the new row for Symbol 1BnRDI and changed `7-4' to `7-5' for Bit column in first row of table. Modified Description column for Symbol TCnEN. Removed second hyphen from device part number (now TXC-04252AIPQ). Added Figure 29. Added Part Number for PBGA under Ordering Information section. Updated Standard Documentation Sources section. Updated List of Data Sheet Changes section. Updated Documentation Update Registration Form.
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DATA SHEET - NOTES -
QE1M TXC-04252
TranSwitch reserves the right to make changes to the product(s) or circuit(s) described herein without notice. No liability is assumed as a result of their use or application. TranSwitch assumes no liability for TranSwitch applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TranSwitch warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TranSwitch covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.
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TranSwitch Corporation
*
3 Enterprise Drive
*
Shelton, CT 06484 USA
*
Tel: 203-929-8810
*
Fax: 203-926-9453
*
www.transwitch.com
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DATA SHEET DOCUMENTATION UPDATE REGISTRATION FORM
QE1M TXC-04252
If you would like to receive updated documentation for selected devices as it becomes available, please provide the information requested below (print clearly or type) then tear out this page, fold and mail it to the Marketing Communications Department at TranSwitch. Marketing Communications will ensure that the relevant Product Information Sheets, Data Sheets, Application Notes, Technical Bulletins and other publications are sent to you. You may also choose to provide the same information by fax (203.926.9453), or by e-mail (info@txc.com), or by telephone (203.929.8810). Most of these documents will also be made immediately available for direct download as Adobe PDF files from the TranSwitch World Wide Web Site (www.transwitch.com). Name: _________________________________________________________________________________ Company: __________________________________________ Title: ______________________________ Dept./Mailstop: __________________________________________________________________________ Street: _________________________________________________________________________________ City/State/Zip: ___________________________________________________________________________ If located outside U.S.A., please add - Country: ________________ Postal Code: ____________________ Telephone: _______________________ Ext.: ____________ Fax: __________________________
E-mail: _______________________________________________ Please provide the following details for the managers in charge of the following departments at your company location. Department Company/Division Engineering Marketing Title __________________ __________________ __________________ Name __________________ __________________ __________________
Please describe briefly your intended application(s) and indicate whether you would like to have a TranSwitch applications engineer contact you to provide further assistance: ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ If you are also interested in receiving updated documentation for other TranSwitch device types, please list them below rather than submitting separate registration forms: __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________
Please fold, tape and mail this page (see other side) or fax it to Marketing Communications at 203.926.9453.
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TXC-04252-MB Ed. 3, December 2000
(Fold back on this line second, then tape closed, stamp and mail.)
3 Enterprise Drive Shelton, CT 06484-4694 U.S.A.
First Class Postage Required
TranSwitch Corporation
Attention: Marketing Communications Dept. 3 Enterprise Drive Shelton, CT 06484-4694 U.S.A.
(Fold back on this line first.)
Please complete the registration form on this back cover sheet, and fax or mail it, if you wish to receive updated documentation on this TranSwitch product as it becomes available.
TranSwitch Corporation
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3 Enterprise Drive
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Shelton, CT 06484 USA
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Tel: 203-929-8810
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Fax: 203-926-9453
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www.transwitch.com

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